公开(公告)号：US20200176471A1

公开(公告)日：2020-06-04

申请号：US16783981

申请日：2020-02-06

Applicant: Micron Technology, Inc.

Inventor： Jie Li ,  James Mathew ,  Kunal Shrotri ,  Luan C. Tran ,  Gordon A. Haller ,  Yangda Zhang ,  Hongpeng Yu ,  Minsoo Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

公开(公告)号：US11195854B2

公开(公告)日：2021-12-07

申请号：US16783981

申请日：2020-02-06

Applicant: Micron Technology, Inc.

Inventor： Jie Li ,  James Mathew ,  Kunal Shrotri ,  Luan C. Tran ,  Gordon A. Haller ,  Yangda Zhang ,  Hongpeng Yu ,  Minsoo Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

公开(公告)号：US20180358378A1

公开(公告)日：2018-12-13

申请号：US16107294

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Jie Li ,  James Mathew ,  Kunal Shrotri ,  Luan C. Tran ,  Gordon A. Haller ,  Yangda Zhang ,  Hongpeng Yu ,  Minsoo Lee

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H05K999/99

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

公开(公告)号：US20170365617A1

公开(公告)日：2017-12-21

申请号：US15679727

申请日：2017-08-17

Applicant: Micron Technology, Inc.

Inventor： Jie Li ,  James Mathew ,  Kunal Shrotri ,  Luan C. Tran ,  Gordon A. Haller ,  Yangda Zhang ,  Hongpeng Yu ,  Minsoo Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

公开(公告)号：US20140027832A1

公开(公告)日：2014-01-30

申请号：US14043943

申请日：2013-10-02

Applicant: Micron Technology, Inc.

Inventor： James Mathew ,  Gordon Haller ,  Ronald A. Weimer ,  John Hopkins ,  Vinayak K. Shamanna ,  Sanjeev Sapra

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/764 ,  H01L27/11524 ,  H01L27/1157

Abstract: A memory array has first and second memory cells over a semiconductor and an isolation region extending into the semiconductor. The isolation region includes an air gap between charge-storage structures of the first and second memory cells and a thickness of dielectric over the air gap and contained between the first and second memory cells.

Abstract translation: 存储器阵列具有半导体上的第一和第二存储器单元以及延伸到半导体中的隔离区。 隔离区包括第一和第二存储单元的电荷存储结构之间的气隙和气隙上的电介质的厚度，并且包含在第一和第二存储单元之间。

公开(公告)号：US10083984B2

公开(公告)日：2018-09-25

申请号：US15679727

申请日：2017-08-17

Applicant: Micron Technology, Inc.

Inventor： Jie Li ,  James Mathew ,  Kunal Shrotri ,  Luan C. Tran ,  Gordon A. Haller ,  Yangda Zhang ,  Hongpeng Yu ,  Minsoo Lee

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H05K999/99

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

公开(公告)号：US09773805B1

公开(公告)日：2017-09-26

申请号：US15187632

申请日：2016-06-20

Applicant: Micron Technology, Inc.

Inventor： Jie Li ,  James Mathew ,  Kunal Shrotri ,  Luan C. Tran ,  Gordon A. Haller ,  Yangda Zhang ,  Hongpeng Yu ,  Minsoo Lee

IPC: H01L29/51 ,  H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

公开(公告)号：US08575716B2

公开(公告)日：2013-11-05

申请号：US13893454

申请日：2013-05-14

Applicant: Micron Technology, Inc.

Inventor： James Mathew ,  Brett D. Lowe ,  Yunjun Ho ,  H. Jim Fulford ,  Jie Sun ,  Zhaoli Sun

IPC: H01L21/70

CPC classification number: H01L29/0649 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/76229 ,  H01L27/11526 ,  H01L27/11573

Abstract: A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches. Other aspects are disclosed, including integrated circuitry resulting from the disclosed methods and integrated circuitry independent of method of manufacture.

公开(公告)号：US10580792B2

公开(公告)日：2020-03-03

申请号：US16107294

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Jie Li ,  James Mathew ,  Kunal Shrotri ,  Luan C. Tran ,  Gordon A. Haller ,  Yangda Zhang ,  Hongpeng Yu ,  Minsoo Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

公开(公告)号：US09397210B2

公开(公告)日：2016-07-19

申请号：US14043943

申请日：2013-10-02

Applicant: Micron Technology, Inc.

Inventor： James Mathew ,  Gordon Haller ,  Ronald A. Weimer ,  John Hopkins ,  Vinayak K. Shamanna ,  Sanjeev Sapra

IPC: H01L27/115 ,  H01L29/78 ,  H01L21/764

CPC classification number: H01L29/78 ,  H01L21/764 ,  H01L27/11524 ,  H01L27/1157

Abstract: A memory array has first and second memory cells over a semiconductor and an isolation region extending into the semiconductor. The isolation region includes an air gap between charge-storage structures of the first and second memory cells and a thickness of dielectric over the air gap and contained between the first and second memory cells.

Abstract translation: 存储器阵列具有半导体上的第一和第二存储器单元以及延伸到半导体中的隔离区。 隔离区包括第一和第二存储单元的电荷存储结构之间的气隙和气隙上的电介质的厚度，并且包含在第一和第二存储单元之间。