公开(公告)号：US20160104533A1

公开(公告)日：2016-04-14

申请号：US14509953

申请日：2014-10-08

Applicant: Micron Technology, Inc.

Inventor： TORU TANZAWA ,  Aaron Yip

IPC: G11C16/04 ,  G11C16/10

CPC classification number: G11C16/28 ,  G11C7/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3427

Abstract: Apparatuses and methods for reducing capacitive loading are described. An example apparatus may include a plurality of memory subblocks of a memory block. A. plurality of word lines may be associated with the plurality of subblocks. The word lines may be further associated with multiple strings within the subblocks. A subset of the word lines may be dummy word lines. The cells of the dummy word lines may be programmed to a plurality of states. The states may be configured to deactivate and/or float unselected strings in the subblocks during certain memory operations.

Abstract translation: 描述了用于降低电容负载的装置和方法。 示例性装置可以包括存储器块的多个存储器子块。 多个字线可以与多个子块相关联。 字线可以进一步与子块内的多个字符串相关联。 字线的子集可以是虚拟字线。 虚拟字线的单元可以被编程为多个状态。 可以将状态配置为在某些存储器操作期间停用和/或浮动子块中未选择的字符串。

公开(公告)号：US20170069392A1

公开(公告)日：2017-03-09

申请号：US14846549

申请日：2015-09-04

Applicant: Micron Technology, Inc.

Inventor： TORU TANZAWA

IPC: G11C16/26 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

Abstract: Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a memory. A plurality of global access lines may be associated with the memory array. The global access line may be charged to a ready-access voltage before any access command has been received by the memory. The global access line may be maintained at the ready-access voltage during memory access operations until the receipt of a post-access command. The post-access command may reset the global access line to an inactive voltage.

Abstract translation: 描述了在访问存储器之前对全局访问线进行充电的装置和方法。 示例性装置可以包括存储器的存储器阵列。 多个全局访问线路可以与存储器阵列相关联。 在存储器已经接收到任何访问命令之前，全局访问线路可能被充电到准备就绪电压。 在存储器访问操作期间，全局访问线路可以保持在就绪访问电压，直到接收到后访问命令。 后访问命令可以将全局访问线路重置为无效电压。

公开(公告)号：US20150023104A1

公开(公告)日：2015-01-22

申请号：US13946841

申请日：2013-07-19

Applicant: Micron Technology, Inc.

Inventor： TORU TANZAWA

IPC: G11C29/02 ,  G01R31/28

CPC classification number: G06F17/5036 ,  G11C7/1066 ,  G11C7/227 ,  G11C13/0021 ,  G11C29/025

Abstract: Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal line. The apparatus further includes a measurement circuit coupled to the signal line model and configured to measure the electrical characteristic of the model signal line responsive to an input signal provided to the model signal line. The measurement circuit is further configured to provide measurement information based at least in part on the measurement to set a signal applied to the signal line.

Abstract translation: 用于测量模型信号线的电特性并且至少部分地基于电特性的测量提供测量信息的装置和方法。 示例性装置包括信号线模型，其包括被配置为模拟信号线的电特性的模型信号线。 该装置还包括耦合到信号线模型并被配置为响应于提供给模型信号线的输入信号来测量模型信号线的电特性的测量电路。 测量电路还被配置为至少部分地基于测量来提供测量信息，以设置施加到信号线的信号。

公开(公告)号：US20180358099A1

公开(公告)日：2018-12-13

申请号：US16046527

申请日：2018-07-26

Applicant: MICRON TECHNOLOGY , INC.

Inventor： TORU TANZAWA

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C16/32 ,  G11C16/30

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  G11C16/32

Abstract: Apparatuses and methods for charging a global access line prior to accessing memory are described. An example apparatus may include a memory array of a memory. A plurality of global access lines may be associated with the memory array. The global access line may be charged to a ready-access voltage before any access command has been received by the memory. The global access line may be maintained at the ready-access voltage during memory access operations until the receipt of a post-access command. The post-access command may reset the global access line to an inactive voltage.

公开(公告)号：US20170131904A1

公开(公告)日：2017-05-11

申请号：US14933874

申请日：2015-11-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SHANTANU R. RAJWADE ,  PRANAV KALAVADE ,  TORU TANZAWA

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/16 ,  G06F13/42

Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

公开(公告)号：US20190318788A1

公开(公告)日：2019-10-17

申请号：US16454263

申请日：2019-06-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TORU TANZAWA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08

Abstract: Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a memory. A plurality of global access lines may be associated with the memory array. The global access line may be charged to a ready-access voltage before any access command has been received by the memory. The global access line may be maintained at the ready-access voltage during memory access operations until the receipt of a post-access command. The post-access command may reset the global access line to an inactive voltage.

公开(公告)号：US20190221272A1

公开(公告)日：2019-07-18

申请号：US16366201

申请日：2019-03-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TORU TANZAWA ,  AARON YIP

IPC: G11C16/28 ,  G11C16/08 ,  G11C16/24 ,  G11C7/02 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/28 ,  G11C7/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3427

Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.