公开(公告)号：US10936038B2

公开(公告)日：2021-03-02

申请号：US16457304

申请日：2019-06-28

Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

Inventor： Bryan Kelly ,  Mark Santaniello ,  Sriram Govindan ,  Anirudh Badam

IPC: G06F1/32 ,  G06F1/26 ,  G06F3/06 ,  G06F1/3206 ,  G06F1/3212 ,  G06F1/3234 ,  G06F1/3287

Abstract: A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.

公开(公告)号：US10199669B2

公开(公告)日：2019-02-05

申请号：US15143590

申请日：2016-05-01

Applicant: Microsoft Technology Licensing, LLC

Inventor： Di Wang ,  Sriram Govindan ,  John J. Siegler ,  Jie Liu ,  Ricardo Bianchini ,  Eric Peterson ,  Sean M. James ,  Bryan Kelly

IPC: H01M8/04 ,  H01M8/04664 ,  G01R31/36 ,  G01R19/00 ,  G06F1/28 ,  H02J7/00 ,  H01M8/04858 ,  H01M8/04537 ,  H01M8/04746

Abstract: A fuel cell power controller tracks load current and fuel cell output voltage, and alerts on excessive fuel cell ramp rate, so another power source can supplement the fuel cell and/or the load can be reduced. A power engineering process makes efficient use of available fuel cell power by ramping up power flow rapidly when power is available, while respecting the ramp rate and other power limitations of the fuel cell and safety limitations of the load. Power flow decreases after an alert indicating an electrical output limitation of the fuel cell. Permitted power flow increases in response to a power demand increase (actual or requested) from the load in the absence of the alert. Power flow may increase or decrease in a fixed amount, a proportional amount, or per a sequence. A power controller relay may trip open on a low fuel cell output voltage or high load current.

公开(公告)号：US09760147B2

公开(公告)日：2017-09-12

申请号：US15004866

申请日：2016-01-22

Applicant: Microsoft Technology Licensing, LLC

Inventor： Bryan Kelly ,  Mark Santaniello ,  Sriram Govindan ,  Anirudh Badam

IPC: G06F1/32 ,  G06F1/26 ,  G06F3/06

CPC classification number: G06F1/3206 ,  G06F1/263 ,  G06F1/3212 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0685 ,  Y02D10/14 ,  Y02D10/152 ,  Y02D10/154 ,  Y02D10/171 ,  Y02D10/174

Abstract: A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.

公开(公告)号：US10528113B2

公开(公告)日：2020-01-07

申请号：US15811015

申请日：2017-11-13

Applicant: Microsoft Technology Licensing, LLC

Inventor： Bryan D. Kelly ,  Badriddine Khessib ,  Sriram Govindan

IPC: G06F1/3234 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/30 ,  G06F1/3206

Abstract: Technology for handling overcurrent conditions on electrical circuits that power multiple computing modules is disclosed. Aspects of the technology include a power system adapted to provide notifications of overcurrent conditions, and computing modules adapted to reduce an operating speed thereof in response to notification of an overcurrent condition.

公开(公告)号：US10168756B2

公开(公告)日：2019-01-01

申请号：US15274884

申请日：2016-09-23

Applicant: Microsoft Technology Licensing, LLC

Inventor： Badriddine Khessib ,  Bryan Kelly ,  Mark Santaniello ,  Chris Ong ,  John Siegler ,  Sriram Govindan ,  Shaun Harris

IPC: G06F11/00 ,  G06F1/26 ,  G06F1/30 ,  G06F1/32 ,  G06F9/4401 ,  G06F12/0804

Abstract: Various techniques for managing power backup for computing devices are disclosed herein. In one embodiment, a method includes receiving data representing a backup capacity of one or more backup power units and data representing a backup power profile of one or more processing units sharing the one or more backup power units. A portion of the backup capacity may then be assigned to each of the one or more processing units based at least in part on both the received data representing the backup capacity of the one or more backup power units and the received data representing the profile of the one or more processing units.

公开(公告)号：US10031801B2

公开(公告)日：2018-07-24

申请号：US14956335

申请日：2015-12-01

Applicant: Microsoft Technology Licensing, LLC

Inventor： Sriram Govindan ,  Bryan Kelly

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06

Abstract: Technology relating to configurable reliability schemes for memory devices is disclosed. The technology includes a memory controller that selectively controls at least a type or an extent of a reliability scheme for at least a portion of a memory device. The technology also includes a computing device that can dynamically select and employ reliability schemes from a collection of different reliability schemes. A reliability scheme may be selected on a per-process, per-allocation request, per-page, per-cache-line, or other basis. The reliability schemes may include use of parity, use of data mirroring, use of an error correction code (ECC), storage of data without redundancy, etc.

公开(公告)号：US20180107596A1

公开(公告)日：2018-04-19

申请号：US15406933

申请日：2017-01-16

Applicant: Microsoft Technology Licensing, LLC

Inventor： Bryan Kelly ,  Bikash Sharma ,  Anirudh Badam ,  Sriram Govindan ,  Rajat Kateja

IPC: G06F12/0804 ,  G06F1/26 ,  G06F1/30 ,  G06F9/30 ,  G06F11/07

CPC classification number: G06F12/0804 ,  G06F1/30 ,  G06F9/3004 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0793 ,  G06F2212/1032 ,  G06F2212/205

Abstract: Embodiments of battery-based data persistence management in computing devices are disclosed therein. In one embodiment, a method includes receiving a storage request to persistently store data in the computing device. In response to receiving the storage request, the method includes allocating a number of memory blocks of the main memory to store the data associated with the storage request and incrementing an accumulated number of memory blocks in the main memory that contain data stored in response to received storage requests. The method further includes maintaining the accumulated number of memory blocks in the main memory below a threshold corresponding to an energy capacity of the auxiliary power source and copying all of the stored data in the memory blocks of the main memory to the persistent storage using power from only the auxiliary power source when the main power supply suffers an unexpected power failure.

公开(公告)号：US09746895B2

公开(公告)日：2017-08-29

申请号：US15004830

申请日：2016-01-22

Applicant: Microsoft Technology Licensing, LLC

Inventor： Bryan Kelly ,  Mark Santaniello ,  Sriram Govindan ,  Anirudh Badam

IPC: G06F1/28 ,  G06F3/06

CPC classification number: G06F1/28 ,  G06F3/0619 ,  G06F3/0631 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0685 ,  G06F3/0688 ,  G06F3/0689

Abstract: A computing device may comprise a processor, a volatile memory and a non-volatile storage device. An operating system or firmware of the device may cause one or more pages of the volatile memory to be treated, by applications executing on the computing device, as non-volatile memory pages. A maximum number of pages that may be treated as non-volatile may be determined based on an amount of energy available in a battery and an amount of energy needed to transfer a page of memory to the non-volatile storage device.

公开(公告)号：US20170206026A1

公开(公告)日：2017-07-20

申请号：US15002216

申请日：2016-01-20

Applicant: Microsoft Technology Licensing, LLC

Inventor： Iyswarya Narayanan ,  Di Wang ,  Myeongjae Jeon ,  Bikash Sharma ,  Laura Marie Caulfield ,  Sriram Govindan ,  Benjamin Franklin Cutler ,  Christopher W. Hoder ,  Jaya Naga Satish Bobba ,  Jie Liu ,  Badriddine Khessib

IPC: G06F3/06

CPC classification number: G06F3/0614 ,  G06F3/0605 ,  G06F3/0616 ,  G06F3/0631 ,  G06F3/067 ,  G06F3/0679 ,  G06F3/0683

Abstract: Aspects extend to methods, systems, and computer program products for predicting solid state drive reliability. Aspects of the invention can be used to predict and/or to configure a data center to minimize one or more of: SSD capacity degradation (how much storage an SSD has left), SSD performance degradation (reduced read/write latency/throughput), and SSD failure. Models and data center considerations can be based on device level SSD related operations, such as, for example, read, write, erase. Operations decisions can be made for a data center based on SSD specific features, such as, for example, remaining capacity, write amplification factor, etc. Dependence and/or causality of various different data center factors can be leveraged. The impact of the various data center factors on different SSD failure modes and capacity/performance degradation can be quantified to drive SSD design, SSD provisioning, and SSD operations.

公开(公告)号：US10338659B2

公开(公告)日：2019-07-02

申请号：US15666255

申请日：2017-08-01

Applicant: Microsoft Technology Licensing, LLC

Inventor： Bryan Kelly ,  Mark Santaniello ,  Sriram Govindan ,  Anirudh Badam

IPC: G06F1/32 ,  G06F1/26 ,  G06F3/06 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3212

Abstract: A computing device may comprise a volatile memory and a non-volatile storage device. Upon system shutdown, contents of the volatile memory may be preserved by memory transfer operations from the volatile memory to the non-volatile storage device. During memory preservation, the computing device may enter a low-power state. The low-power state may comprise suspension of power to a core of a processor while maintaining power to the processor's uncore, and disablement of interrupt signals not related to memory transfer operations. Power delivery to the core of the processor may be periodically resumed to initiate additional memory transfer operations.