公开(公告)号：US06469359B2

公开(公告)日：2002-10-22

申请号：US09760885

申请日：2001-01-17

申请人： Mietek Bakowski ,  Ulf Gustafsson ,  Heinz Lendenmann

发明人： Mietek Bakowski ,  Ulf Gustafsson ,  Heinz Lendenmann

IPC分类号： H01L2358

CPC分类号： H01L29/66068 ,  H01L29/1608 ,  H01L29/7722 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device of planar structure has a pn-junction (10) formed by a first layer (1) doped according to a first conductivity type, n or p, and on top thereof a second layer (2) doped according to a second conductivity type. The second layer has a higher doping concentration than the first layer and a lateral edge thereof is provided with an edge termination with second zones of said second conductivity type separated by first zones (4) of said first conductivity type arranged so that the total charge and/or the effective sheet charge density of dopants according to said second conductivity type is decreasing towards the laterally outer border (8) of the edge termination. A third layer (5) doped according to said first conductivity type is arranged on top of said second layer at least in the region of the edge termination for burying the edge termination of the device thereunder.

摘要翻译： 平面结构的半导体器件具有由根据第一导电类型n或p掺杂的第一层（1）形成的pn结（10），并且在其顶部上具有根据第二导电性掺杂的第二层（2） 类型。 第二层具有比第一层更高的掺杂浓度，并且其侧边缘设置有边缘终端，其中所述第二导电类型的第二区被所述第一导电类型的第一区（4）隔开，以使总电荷和 /或根据所述第二导电类型的掺杂剂的有效片电荷密度朝着边缘终端的横向外边界（8）减小。 根据所述第一导电类型掺杂的第三层（5）至少在边缘终端的区域中布置在所述第二层的顶部上，用于掩埋其下方的器件的边缘终端。

公开(公告)号：US5932894A

公开(公告)日：1999-08-03

申请号：US883106

申请日：1997-06-26

申请人： Mietek Bakowski ,  Ulf Gustafsson ,  Christopher I. Harris

发明人： Mietek Bakowski ,  Ulf Gustafsson ,  Christopher I. Harris

IPC分类号： H01L29/06 ,  H01L29/12 ,  H01L29/24 ,  H01L29/739 ,  H01L29/76 ,  H01L29/78 ,  H01L29/80 ,  H01L29/861 ,  H01L31/0256 ,  H01L31/0312

CPC分类号： H01L29/1608 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/7606

摘要： A semiconductor device of planar structure, comprises a pn junction, formed of a first type conducting layer and on top thereof a second type conducting layer, both layers of doped silicon carbide, the edge of the second of the layers being provided with an edge termination (JTE), enclosing stepwise or continuously decreasing effective sheet charge density towards the outer border of the termination, wherein the pn junction and its JTE are covered by a doped or undoped SiC third layer.

摘要翻译： 平面结构的半导体器件包括由第一类型导电层形成的pn结，并且在其顶部具有第二导电层，两层掺杂碳化硅，第二层的边缘设置有边缘终端 （JTE），围绕端接的外边界逐步或连续地降低有效片电荷密度，其中pn结及其JTE由掺杂或未掺杂的SiC第三层覆盖。

公开(公告)号：US6002159A

公开(公告)日：1999-12-14

申请号：US683059

申请日：1996-07-16

申请人： Mietek Bakowski ,  Ulf Gustafsson ,  Kurt Rottner ,  Susan Savage

发明人： Mietek Bakowski ,  Ulf Gustafsson ,  Kurt Rottner ,  Susan Savage

IPC分类号： H01L29/861 ,  H01L21/04 ,  H01L29/06 ,  H01L29/24 ,  H01L23/58

CPC分类号： H01L29/0619 ,  H01L21/0465 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/6606 ,  H01L2924/0002 ,  Y10S438/931

摘要： A semiconductor component including a silicon carbide substrate. A pn junction includes doped layers of the substrate. The pn junction includes at a surface of the substrate a low doped first conductivity type layer and at a portion of the surface of the substrate a highly doped second conductivity type layer. An edge termination region of the pn junction laterally surrounds the pn junction provided at an edge of at least one of the layers of the pn junction. The edge termination region includes zones of the second conductivity type located at an edge of the highly doped second conductivity type layer. A charge content of the zones decreases toward an edge of the edge termination region in accordance with at least one characteristic selected from the group consisting of a stepwise or continuously decreasing total charge towards an outer border of the edge termination region and a decreasing effective sheet charge density toward an outer border of the edge termination region. An outermost zone of the edge termination region is completely depleted at full design voltage.

摘要翻译： 包括碳化硅衬底的半导体部件。 pn结包括衬底的掺杂层。 pn结在衬底的表面上包括低掺杂的第一导电类型层，并且在衬底的表面的一部分处包括高度掺杂的第二导电类型层。 pn结的边缘终止区横向地围绕设置在pn结的至少一个层的边缘处的pn结。 边缘终止区域包括位于高度掺杂的第二导电类型层的边缘处的第二导电类型的区域。 根据从边缘终止区域的外边界逐步或连续减小的总电荷和降低的有效片材电荷的组中选出的至少一个特征，区域的电荷含量朝向边缘终止区域的边缘减小 密度朝向边缘终止区域的外边界。 边缘终端区域的最外区域在完全设计电压下完全耗尽。

公开(公告)号：US5801836A

公开(公告)日：1998-09-01

申请号：US680921

申请日：1996-07-16

申请人： Mietek Bakowski ,  Ulf Gustafsson

发明人： Mietek Bakowski ,  Ulf Gustafsson

IPC分类号： H01L21/04 ,  H01L29/06 ,  H01L29/24 ,  H01L23/58 ,  H01L29/861

CPC分类号： H01L29/1608 ,  H01L21/0465 ,  H01L29/0603 ,  H01L29/6606 ,  H01L2924/0002

摘要： A semiconductor component comprises a pn junction having a first conductivity type layer and a second conductivity type layer, both being doped layers of silicon carbide (SiC), the first conductivity type layer being lower doped and being provided with a depletion region stopper (DRS) located outside the pn junction, the DRS having stepwise or continuously increasing effective sheet charge density of the first conducting type in a radial direction towards the outer edge of the semiconductor component.

摘要翻译： 半导体部件包括具有第一导电类型层和第二导电类型层的pn结，二者均为碳化硅（SiC）的掺杂层，第一导电类型层较低掺杂并且设置有耗尽区域阻挡层（DRS） 位于pn结外部，DRS具有逐渐或连续增加的第一导电类型的有效片电荷密度，朝向半导体部件的外边缘的径向方向。

公开(公告)号：US06313488B1

公开(公告)日：2001-11-06

申请号：US09333296

申请日：1999-06-15

申请人： Mietek Bakowski ,  Bo Breitholtz ,  Ulf Gustafsson ,  Lennart Zdansky

发明人： Mietek Bakowski ,  Bo Breitholtz ,  Ulf Gustafsson ,  Lennart Zdansky

IPC分类号： H01L29737

CPC分类号： H01L29/1004 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/7371 ,  H01L29/739

摘要： A bipolar transistor having at least a low doped drift layer (14) of crystalline SiC comprises at least one first layer (13) of a semi-conductor material having a wider energy gap between the conduction band and the valence band than an adjacent layer (14) of SiC.

摘要翻译： 具有晶体SiC的至少低掺杂漂移层（14）的双极晶体管包括半导体材料的至少一个第一层（13），其在导带和价带之间具有比相邻层更宽的能隙（ 14）。

公开(公告)号：US5831287A

公开(公告)日：1998-11-03

申请号：US706264

申请日：1996-09-04

申请人： Mietek Bakowski ,  Ulf Gustafsson ,  Henry Bleichner

发明人： Mietek Bakowski ,  Ulf Gustafsson ,  Henry Bleichner

IPC分类号： H01L21/04 ,  H01L29/24 ,  H01L29/739 ,  H01L31/0312

CPC分类号： H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7395

摘要： A bipolar semiconductor comprising layers of SiC semiconductor material. At least one pn-junction is formed between two of the layers having charged carrier transport across the junction when the device is in a conductive state. A resistive element in series with the pn-junction lowers the current through the pn-junction as the voltage drop across the device increases with an increase in temperature. The temperature coefficient for the device switches from a negative to a positive at a lower current through the device.

摘要翻译： 包括SiC半导体材料层的双极半导体。 当器件处于导通状态时，在具有带电荷的载流子传输跨越结的两个层之间形成至少一个pn结。 与pn结串联的电阻元件随着温度的升高随着器件上的电压降而降低通过pn结的电流。 器件的温度系数从负值切换到低电流通过器件的正温度。

公开(公告)号：US5773849A

公开(公告)日：1998-06-30

申请号：US636940

申请日：1996-04-24

申请人： Christopher Harris ,  Mietek Bakowski ,  Ulf Gustafsson ,  Mats Andersson

发明人： Christopher Harris ,  Mietek Bakowski ,  Ulf Gustafsson ,  Mats Andersson

IPC分类号： H01L21/04 ,  H01L29/24 ,  H01L29/739 ,  H01L29/745 ,  H01L29/749 ,  H01L31/0312

CPC分类号： H01L29/1608 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7455 ,  H01L29/749

摘要： A field controlled semiconductor device of SiC has a drain, a highly doped substrate layer on top of the drain and a low doped n-type drift layer on top of the substrate layer. A p-type base layer is located on the drift layer and a vertical trench extends through the base layer. In the trench an n-type channel region extends vertically along a wall of the trench and connects a source region layer to the drift layer. A gate electrode is arranged in the trench to be on the opposite side of the channel region with respect to the base layer.

摘要翻译： SiC的场控半导体器件具有漏极，在漏极顶部具有高度掺杂的衬底层，在衬底层的顶部具有低掺杂的n型漂移层。 p型基层位于漂移层上，垂直沟槽延伸通过基层。 在沟槽中，n型沟道区域沿着沟槽的壁垂直延伸，并将源极区域层连接到漂移层。 沟槽中布置有栅电极，以相对于基层在通道区域的相对侧。

公开(公告)号：US06201280B1

公开(公告)日：2001-03-13

申请号：US09019715

申请日：1998-02-06

申请人： Mietek Bakowski ,  Ulf Gustafsson

发明人： Mietek Bakowski ,  Ulf Gustafsson

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/7397

摘要： A transistor of SiC for high voltage and high switching frequency applications is a MISFET or an IGBT. This transistor comprises a plurality of laterally spaced active regions. The center to center distance of two adjacent active regions defines a lateral width of a cell of the transistor. The relation of the lateral width of an accumulation region defined as the region in the drift layer connecting to a gate-insulating layer in each individual cell and the lateral cell width is selected so as to keep the power losses in the transistor as a consequence of switching below a determined proportion to the power losses relating to conduction of the transistor for a predetermined switching frequency and on-state voltage for which the transistor is designed.

摘要翻译： 用于高压和高开关频率应用的SiC晶体管是MISFET或IGBT。 该晶体管包括多个横向间隔开的有源区。 两个相邻有源区域的中心到中心距离限定晶体管的单元的横向宽度。 选择定义为连接到每个单电池中的栅极绝缘层的漂移层中的区域的横向宽度与横向电池宽度之间的关系，以便将晶​​体管中的功率损耗保持为 在与晶体管设计的预定开关频率和导通状态电压相关的与晶体管的导通相关的功率损耗下，切换低于确定的比例。

公开(公告)号：US6150671A

公开(公告)日：2000-11-21

申请号：US636943

申请日：1996-04-24

申请人： Christopher Harris ,  Ulf Gustafsson ,  Mietek Bakowski

发明人： Christopher Harris ,  Ulf Gustafsson ,  Mietek Bakowski

IPC分类号： H01L21/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/24 ,  H01L29/78 ,  H01L29/22

CPC分类号： H01L29/7813 ,  H01L29/66068 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  Y10S438/931

摘要： A transistor of SiC having a drain and a highly doped substrate layer is formed on the drain. A highly n type buffer layer may optionally be formed on the substrate layer. A low doped n-type drift layer, a p-type base layer, a high doped n-type source region layer and a source are formed on the substrate layer. An insulating layer with a gate electrode is arranged on top of the base layer and extends substantially laterally from at least the source region layer to a n-type layer. When a voltage is applied to the gate electrode, a conducting inversion channel is formed extending substantially laterally in the base layer at an interface of the p-type base layer and the insulating layer. The p-type base layer is low doped in a region next to the interface to the insulating layer at which the inversion channel is formed and highly doped in a region thereunder next to the drift layer.

摘要翻译： 在漏极上形成具有漏极和高掺杂衬底层的SiC晶体管。 可以可选地在衬底层上形成高度n型缓冲层。 在衬底层上形成低掺杂n型漂移层，p型基极层，高掺杂n型源区域层和源极。 具有栅极电极的绝缘层布置在基层的顶部上，并且至少从源极区域基本上横向延伸到n型层。 当向栅电极施加电压时，在p型基极层和绝缘层的界面处，在基极层中基本上横向延伸形成导电反转沟道。 p型基层在与形成反型沟道的绝缘层的界面旁边的区域中低掺杂，并且在漂移层旁边的区域中高度掺杂。

公开(公告)号：US6091108A

公开(公告)日：2000-07-18

申请号：US971682

申请日：1997-11-17

申请人： Christopher Harris ,  Bo Bijlenga ,  Lennart Zdansky ,  Ulf Gustafsson ,  Mietek Bakowski ,  Andrey Konstantinov

发明人： Christopher Harris ,  Bo Bijlenga ,  Lennart Zdansky ,  Ulf Gustafsson ,  Mietek Bakowski ,  Andrey Konstantinov

IPC分类号： H01L29/16 ,  H01L21/04 ,  H01L29/06 ,  H01L29/12 ,  H01L29/24 ,  H01L29/78 ,  H01L29/745

CPC分类号： H01L29/66068 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device of SiC is adapted to hold high voltages in the blocking state thereof. The device comprises two parts (1, 2) each comprising one or more semiconductor layers of SiC and connected in series between two opposite terminals of the device, namely a sub-semiconductor device (1) able to withstand only low voltages in the blocking state thereof and a voltage-limiting part (2) able to withstand high voltages in the blocking state of the device and adapted to protect said sub-semiconductor device by taking a major part of the voltage over the device in the blocking state thereof.

摘要翻译： SiC的半导体器件适于在其阻挡状态下保持高电压。 该器件包括两个部分（1,2），每个部分包括一个或多个SiC半导体层，并且串联连接在器件的两个相对端子之间，即能够仅承受阻塞状态的低电压的子半导体器件（1） 以及能够承受器件的阻断状态下的高电压的电压限制部分（2），并且适用于通过在其阻塞状态下将器件的大部分电压占据主要部分来保护所述次半导体器件。