公开(公告)号：US6060742A

公开(公告)日：2000-05-09

申请号：US334080

申请日：1999-06-16

申请人： Min-hwa Chi ,  Min-Chie Jung

发明人： Min-hwa Chi ,  Min-Chie Jung

IPC分类号： H01L29/788 ,  H01L29/76 ,  G11C14/00

CPC分类号： H01L29/7885

摘要： An ETOX cell that has improved injection of electrons from a forward biased deep n-well to p-well junction underneath the channel area of a triple-well ETOX cell during substrate hot electron (SHE) programming. The ETOX cell has a control gate, a floating gate, a deep n-well formed in the substrate, a buried n+ layer in the deep n-well, a p-well formed in the n-well and atop the buried n+ layer, a drain implant formed in the p-well, and a source implant formed in the p-well. The buried n+ layer enhances the parasitic bipolar action between the n+ source/drain (as collector), the p-well (as base), and the buried n+ layer (as emitter). The parasitic transistor amplifies the amount of seed electrons injected into the p-well, which in turn results in significantly faster programming of the ETOX cell.

摘要翻译： 在衬底热电子（SHE）编程期间，ETOX电池已经从三阱ETOX电池的通道区域的正向偏置的深n阱到p阱结点改进了电子注入。 ETOX单元具有控制栅极，浮置栅极，在衬底中形成的深n阱，深n阱中的掩埋n +层，在n阱中形成的p阱以及掩埋的n +层顶部， 形成在p阱中的漏极注入，以及形成在p阱中的源极注入。 掩埋的n +层增强了n +源极/漏极（作为集电极），p阱（作为基极）和掩埋的n +层（作为发射极）之间的寄生双极性作用。 寄生晶体管放大注入到p阱中的种子电子的量，这又导致ETOX细胞的编程显着更快。

公开(公告)号：US08264863B2

公开(公告)日：2012-09-11

申请号：US12869941

申请日：2010-08-27

申请人： Min-hwa Chi ,  Deyuan Xiao

发明人： Min-hwa Chi ,  Deyuan Xiao

IPC分类号： G11C11/22

CPC分类号： H01L27/1203 ,  B82Y10/00 ,  G11C11/22 ,  G11C11/223 ,  H01L21/28291 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391

摘要： The present disclosure provides a green transistor for nano-Si Ferro-electric random access memory (FeRAM) and method of operating the same. The nano-Si FeRAM includes a plurality of memory cells arranged in an array with bit-lines and word-lines, and each memory cell includes a MOSFET including a gate, a source, a drain, a substrate, and a data storage element formed on the drain spacer of the gate and made of nano-Si in porous SiO2; a word-line connected to the gate; a first bit-line connected to the drain; a second bit-line connected to the source; and an substrate bias supply connected to the substrate, and the gate induced drain leakage current of the MOSFET serves as the read current of the memory cell.

摘要翻译： 本公开提供了一种用于纳米Si铁电随机存取存储器（FeRAM）的绿色晶体管及其操作方法。 纳米SiFeRAM包括以位线和字线布置成阵列的多个存储单元，并且每个存储单元包括MOSFET，其包括栅极，源极，漏极，衬底和形成的数据存储元件 在栅极的漏极间隔，并由多孔SiO2中的纳米Si制成; 连接到门的字线; 连接到漏极的第一位线; 连接到源的第二位线; 以及连接到衬底的衬底偏置电源，并且MOSFET的栅极感应漏极漏电流用作存储器单元的读取电流。

公开(公告)号：US20110063888A1

公开(公告)日：2011-03-17

申请号：US12861622

申请日：2010-08-23

申请人： Min-hwa Chi ,  Deyuan Xiao

发明人： Min-hwa Chi ,  Deyuan Xiao

IPC分类号： G11C11/00 ,  H01L29/78

CPC分类号： G11C13/0007 ,  G11C11/5685 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/0475 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2436

摘要： A random access memory includes a plurality of memory cells arrayed in bit-lines and word-lines. Each memory cell comprises a green transistor (gFET) including a gate, a source, and a drain; a switching resistor including a first terminal and a second terminal; and a reference resistor including a third terminal and a fourth terminal. The first terminal of the switching resistor and the third terminal is connected to a bit-line, the second terminal of the switching resistor is connected to the first source of the gFET, the fourth terminal of the reference resistor is connected to the second source of the gFET, and the gate of the gFET is connected to a word-line. The method of operating the RRAM includes a write operation and a read operation The write operation comprises steps of: applying a first voltage to the bit-line to perform a large voltage difference across the bit-line and the drain of the gFET, applying a second voltage to the gate of the gFET to turn on the gFET transiently, and a large current pulse flowing through the switching resistor for changing the resistance state. The read operation comprises steps of: applying a third voltage to the bit-line to perform a small voltage difference across the bit-line and the drain of the gFET, applying a second voltage to the word-line to turn on the gFET, and comparing the current through the switching resistor with the current through the reference resistor so as to read the data stored in the memory cell.

摘要翻译： 随机存取存储器包括以位线和字线排列的多个存储单元。 每个存储单元包括包括栅极，源极和漏极的绿色晶体管（gFET）; 开关电阻器，包括第一端子和第二端子; 以及包括第三端子和第四端子的参考电阻器。 开关电阻器和第三端子的第一端子连接到位线，开关电阻器的第二端子连接到gFET的第一源极，参考电阻器的第四端子连接到第二源极 gFET和gFET的栅极连接到字线。 操作RRAM的方法包括写入操作和读取操作。写入操作包括以下步骤：向位线施加第一电压以在gFET的位线和漏极之间执行大的电压差，施加 第二电压到gFET的栅极，瞬时导通gFET，并且大电流脉冲流过开关电阻器以改变电阻状态。 读取操作包括以下步骤：将第三电压施加到位线，以在gFET的位线和漏极之间执行小的电压差，向字线施加第二电压以导通gFET;以及 将通过开关电阻的电流与通过参考电阻的电流进行比较，以读取存储在存储单元中的数据。

公开(公告)号：US06509606B1

公开(公告)日：2003-01-21

申请号：US09053199

申请日：1998-04-01

申请人： Richard B. Merrill ,  Albert Bergemont ,  Min-hwa Chi

发明人： Richard B. Merrill ,  Albert Bergemont ,  Min-hwa Chi

IPC分类号： H01L29788

CPC分类号： H01L29/7883 ,  G11C2216/10 ,  H01L27/115

摘要： Leakage of a single-poly EPROM cell is prevented by eliminating field oxide isolating the source, channel, and drain from the control gate n-well, and by replacing field oxide surrounding the cell with a heavily doped surface isolation region. The EPROM cell also utilizes a floating gate having an open-rectangular floating gate portion over the control gate region, and a narrow floating gate portion over the channel and intervening silicon substrate. The surface area of the open-rectangular floating gate portion ensures a high coupling ratio with the control gate region. The small width of the narrow floating gate portion prevents formation of a sizeable leakage path between the n-well and the source, channel, and drain. To conserve surface area, the EPROM cell also eliminates the p+ contact region and the PLDD region in the control gate well of the conventional EPROM design. This is permitted because the VTp implant step is masked, permitting the control gate region to operate in accumulation mode during application of 5V programming voltages.

摘要翻译： 通过消除从控制栅极n阱分离源极，沟道和漏极的场氧化物，并且通过用重掺杂的表面隔离区域代替围绕电池的场氧化物来防止单聚EPROM单元的泄漏。 EPROM单元还利用在控制栅极区域上具有开放矩形浮动栅极部分的浮动栅极，以及在沟道上方的窄浮动栅极部分和中间的硅衬底。 开放式矩形浮动栅极部分的表面积确保与控制栅极区域的高耦合率。 窄浮动栅极部分的小宽度防止在n阱和源极，沟道和漏极之间形成相当大的泄漏路径。 为了节省表面积，EPROM单元还消除了常规EPROM设计中控制栅极中的p +接触区域和PLDD区域。 这是允许的，因为VTp注入步骤被屏蔽，允许控制栅极区域在施加5V编程电压期间以累积模式工作。

公开(公告)号：US6088058A

公开(公告)日：2000-07-11

申请号：US865569

申请日：1997-05-29

申请人： Carver A. Mead ,  Tobi Delbruck ,  Min-hwa Chi

发明人： Carver A. Mead ,  Tobi Delbruck ,  Min-hwa Chi

IPC分类号： H04N5/353 ,  H04N5/359 ,  H04N5/369 ,  H04N5/374 ,  H04N3/14 ,  G03B7/00 ,  H04N5/335 ,  H04N9/083

CPC分类号： H04N5/3532 ,  H04N5/353 ,  H04N5/3591 ,  H04N5/3594 ,  H04N5/3741

摘要： An imaging array having overflow protection and electronic shuttering features is realized without an increase in pixel complexity. Overflow protection is provided by pulsing each row of the imager with a small overflow pulse during the sense amplifier reset phase. An electronic shutter is realized using a modified version of the pixel readout timing. The shutter provides sub-frame exposure by restricting the number of line-times a pixel is allowed to integrate. For a full-frame exposure, each pixel is read out once per frame; during readout of the other rows of the array, the pixel integrates. For subframe exposure, the pixel is continually reset, using a shutter pulse applied to the row lines during sense amplifier reset, until a certain number of rows (line-times) before it is to be read out. The pixel then is allowed to integrate until it is read out normally.

摘要翻译： 实现了具有溢出保护和电子快门功能的成像阵列，而不增加像素复杂度。 通过在感测放大器复位阶段期间使成像器的每行脉冲具有小的溢出脉冲来提供溢出保护。 使用像素读出定时的修改版本来实现电子快门。 快门通过限制允许像素集成的行数的次数来提供子帧曝光。 对于全帧曝光，每个像素每帧读出一次; 在读出阵列的其他行期间，像素被整合。 对于子帧曝光，使用在读出放大器复位期间施加到行线的快门脉冲，直到要读出之前的一定数量的行（行时间），像素被连续复位。 然后允许像素整合，直到它被正常读出。

公开(公告)号：US6011295A

公开(公告)日：2000-01-04

申请号：US898062

申请日：1997-07-22

申请人： Richard Billings Merrill ,  Albert Bergemont ,  Min-hwa Chi

发明人： Richard Billings Merrill ,  Albert Bergemont ,  Min-hwa Chi

IPC分类号： G06N3/063 ,  G06G7/16

CPC分类号： G06N3/0635

摘要： An active pixel image cell which includes a photosensor, active devices for control of the sensor and readout of a signal representing the intensity of light to which the sensor is exposed, and a neuron MOSFET transistor which "both amplifies the signal from the photosensor and" simulates the behavior of a human neuron. An integrated neural network and imaging array may be formed by interconnecting a group of such pixels. Digital signal processing algorithms used for image processing may be implemented at the pixel level by appropriate interconnections between the output signals from the photosensor of surrounding pixels and the neuron MOSFET.

摘要翻译： 包括光传感器的有源像素图像单元，用于控制传感器的有源器件和表示传感器所暴露的光的强度的信号的读出，以及“两者都放大来自光电传感器的信号”的神经元晶体管， 模拟人类神经元的行为。 可以通过将一组这样的像素互连来形成集成神经网络和成像阵列。 用于图像处理的数字信号处理算法可以通过来自周围像素的光电传感器的输出信号和神经元MOSFET之间的适当互连在像素级上实现。

公开(公告)号：US5566044A

公开(公告)日：1996-10-15

申请号：US438549

申请日：1995-05-10

申请人： Albert Bergemont ,  Carver A. Mead ,  Min-hwa Chi ,  Hosam Haggag

发明人： Albert Bergemont ,  Carver A. Mead ,  Min-hwa Chi ,  Hosam Haggag

IPC分类号： H01L27/146 ,  H01L31/11 ,  H01G4/06 ,  H01L23/58 ,  H01L31/062 ,  H01L31/18

CPC分类号： H01L31/1105 ,  H01L27/14681

摘要： A technique for decreasing the effective gain of a bipolar phototransistor at high light levels makes the image usable over a greatly extended range of illumination conditions. The effective current gain at high light levels is reduced by fabricating a "non-ideal" emitter, such as by inserting a thin 20 521 tunnel oxide between the emitter and base junction. The tunnel oxide between the emitter and base serves as a variable resistor as well as a good junction for carrier injection from the emitter. The total base voltage is the sum of the oxide voltage and the intrinsic base voltage. At high image intensity, the bipolar phototransistor will gradually enter into the saturation mode, i.e., the base to collector junction is forward biased. The beta is thus reduced. The bias of the collector should be about 0.3-0.8 V higher than the emitter at the 20.ANG. tunnel oxide thickness for optimum operation.

摘要翻译： 降低双极光电晶体管在高光照条件下的有效增益的技术使得图像在大范围的照明条件下可用。 通过制造“非理想”发射器，例如通过在发射极和基极结之间插入薄的20 521隧道氧化物，可以降低高光级的有效电流增益。 发射极和基极之间的隧道氧化物用作可变电阻器，以及用于从发射极注入载流子的良好结。 总基极电压是氧化物电压和本征基极电压之和。 在高图像强度下，双极光电晶体管将逐渐进入饱和模式，即基极到集电极结正向偏置。 因此，beta被减少了。 在20 ANGSTROM隧道氧化物厚度下，集电极的偏压应比发射极高0.3-0.8V，以获得最佳的操作。

公开(公告)号：US20110090731A1

公开(公告)日：2011-04-21

申请号：US12869941

申请日：2010-08-27

申请人： Min-hwa Chi ,  Deyuan Xiao

发明人： Min-hwa Chi ,  Deyuan Xiao

IPC分类号： G11C11/22 ,  H01L27/12

CPC分类号： H01L27/1203 ,  B82Y10/00 ,  G11C11/22 ,  G11C11/223 ,  H01L21/28291 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391

摘要： The present disclosure provides a green transistor for nano-Si Ferro-electric random access memory (FeRAM) and method of operating the same. The nano-Si FeRAM includes a plurality of memory cells arranged in an array with bit-lines and word-lines, and each memory cell includes a MOSFET including a gate, a source, a drain, a substrate, and a data storage element formed on the drain spacer of the gate and made of nano-Si in porous SiO2; a word-line connected to the gate; a first bit-line connected to the drain; a second bit-line connected to the source; and an substrate bias supply connected to the substrate, and the gate induced drain leakage current of the MOSFET serves as the read current of the memory cell.

摘要翻译： 本公开提供了一种用于纳米Si铁电随机存取存储器（FeRAM）的绿色晶体管及其操作方法。 纳米SiFeRAM包括以位线和字线布置成阵列的多个存储单元，并且每个存储单元包括MOSFET，其包括栅极，源极，漏极，衬底和形成的数据存储元件 在栅极的漏极间隔，并由多孔SiO2中的纳米Si制成; 连接到门的字线; 连接到漏极的第一位线; 连接到源的第二位线; 以及连接到衬底的衬底偏置电源，并且MOSFET的栅极感应漏极漏电流用作存储器单元的读取电流。

公开(公告)号：US06288943B1

公开(公告)日：2001-09-11

申请号：US09614411

申请日：2000-07-12

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： G11C1604

CPC分类号： B82Y10/00 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/0458 ,  G11C2211/565 ,  G11C2216/06 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/7887

摘要： A method of reading a 2-bit p-channel memory cell having a p+ drain, a p+ source, a control gate, and a floating gate formed from non-connecting hemispherical silicon grain (HSG) islands. The p+ drain and the p+ source is formed in an n-well. The method comprises: applying a positive voltage to the control gate to generate a gate induced drain leakage (GIDL) current; and measuring a drain GIDL current at the drain and a source GIDL current at the source simultaneously to determine the 2-bit data stored in the memory cell.

摘要翻译： 一种读取具有p +漏极，p +源极，控制栅极和由非连接半球形硅晶粒（HSG）岛形成的浮置栅极的2位p沟道存储单元的方法。 p +漏极和p +源形成在n阱中。 该方法包括：向控制栅极施加正电压以产生栅极感应漏极泄漏（GIDL）电流; 并同时测量漏极处的漏极GIDL电流和源极上的源极GIDL电流，以确定存储在存储器单元中的2位数据。

公开(公告)号：US06255713B1

公开(公告)日：2001-07-03

申请号：US09362916

申请日：1999-07-27

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： H01L2900

CPC分类号： H01L27/0716

摘要： A current source formed in a p-type substrate is disclose. First, a deep n-well is formed within the p-type substrate and a buried n+ layer is formed within the deep n-well. Next, a p-well is formed within the deep n-well and atop the buried n+ layer. The p-well and deep n-well are then surrounded by an isolation structure that extends from the surface of the substrate to below the level of the p-well. A n+ reference structure is formed within the p-well and a gate is formed above the p-well, the gate separated from the substrate by a thin oxide layer, the gate extending over at least a portion of the n+ reference structure. Finally, a n+ output structure is formed within the p-well. An input reference current is provided to the n+ reference structure and an output current is provided by the n+ output structure.

摘要翻译： 公开了形成在p型衬底中的电流源。 首先，在p型衬底内形成深n阱，在深n阱内形成掩埋的n +层。 接下来，在深n阱内和掩埋的n +层顶部形成p阱。 p阱和深n阱然后被从衬底的表面延伸到p阱的水平之下的隔离结构包围。 在p阱内形成n +基准结构，并在p阱的上方形成栅极，栅极通过薄氧化物层与衬底分离，栅极延伸至n +参考结构的至少一部分。 最后，在p阱内形成一个n +输出结构。 输入参考电流提供给n +参考结构，输出电流由n +输出结构提供。