公开(公告)号：US07564136B2

公开(公告)日：2009-07-21

申请号：US11361331

申请日：2006-02-24

申请人： Ming Ling Yeh ,  Chen-Hua Yu ,  Keng-Chu Lin ,  Tien-I Bao ,  Shwang-Ming Cheng

发明人： Ming Ling Yeh ,  Chen-Hua Yu ,  Keng-Chu Lin ,  Tien-I Bao ,  Shwang-Ming Cheng

IPC分类号： H01L23/48

CPC分类号： H01L21/76834 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846

摘要： A semiconductor structure having an opening formed in a porous dielectric layer is provided. The exposed pores of the dielectric layer along the sidewalls of the opening are sealed. The sealing may comprise a selective or a non-selective deposition method. The sealing layer has a substantially uniform thickness in one portion of the opening and a non-uniform thickness in another portion of the opening. A damascene interconnect structure having a pore sealing layer is provided as is its method of manufacture.

摘要翻译： 提供了一种形成在多孔电介质层中的开口的半导体结构。 沿着开口的侧壁的电介质层的暴露的孔被密封。 密封可以包括选择性或非选择性沉积方法。 密封层在开口的一部分中具有基本均匀的厚度，并且在开口的另一部分中具有不均匀的厚度。 如其制造方法那样提供具有孔密封层的镶嵌互连结构。

公开(公告)号：US20070202676A1

公开(公告)日：2007-08-30

申请号：US11361331

申请日：2006-02-24

申请人： Ming Yeh ,  Chen-Hua Yu ,  Keng-Chu Lin ,  Tien-I Bao ,  Shwang-Ming Cheng

发明人： Ming Yeh ,  Chen-Hua Yu ,  Keng-Chu Lin ,  Tien-I Bao ,  Shwang-Ming Cheng

IPC分类号： H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846

摘要： A semiconductor structure having an opening formed in a porous dielectric layer is provided. The exposed pores of the dielectric layer along the sidewalls of the opening are sealed. The sealing may comprise a selective or a non-selective deposition method. The sealing layer has a substantially uniform thickness in one portion of the opening and a non-uniform thickness in another portion of the opening. A damascene interconnect structure having a pore sealing layer is provided as is its method of manufacture.

摘要翻译： 提供了一种形成在多孔电介质层中的开口的半导体结构。 沿着开口的侧壁的电介质层的暴露的孔被密封。 密封可以包括选择性或非选择性沉积方法。 密封层在开口的一部分中具有基本均匀的厚度，并且在开口的另一部分中具有不均匀的厚度。 如其制造方法那样提供具有孔密封层的镶嵌互连结构。

公开(公告)号：US07314828B2

公开(公告)日：2008-01-01

申请号：US11184589

申请日：2005-07-19

申请人： Keng-Chu Lin ,  Chen-Hua Yu ,  Ching-Ya Wang ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Cheng

发明人： Keng-Chu Lin ,  Chen-Hua Yu ,  Ching-Ya Wang ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Cheng

IPC分类号： H01L21/4763

CPC分类号： H01L21/02211 ,  H01L21/0206 ,  H01L21/02074 ,  H01L21/02101 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02334 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76834

摘要： A method of forming a low-k dielectric layer and forming a structure in the low-k dielectric layer includes depositing a low-k dielectric layer over a substrate, performing a first treatment to the low-k dielectric layer, performing post-formation processes, and performing a second treatment to the low-k dielectric layer. The k value of the low-k dielectric layer is lowered by the first treatment. The post-formation processes performed to the low-k dielectric layer include at least one low-k dielectric material damaging process. The second treatment restores the low-k dielectric layer. Preferably, each of the first and second treatments includes a curing process selected from e-beam curing, ultraviolet curing, plasma curing, SCCO2 cleaning, and combinations thereof.

摘要翻译： 形成低k电介质层并在低k电介质层中形成结构的方法包括在衬底上沉积低k电介质层，对低k电介质层进行第一次处理，执行后形成工艺 ，并对低k电介质层进行第二处理。 通过第一次处理，低k电介质层的k值降低。 对低k电介质层进行的后期处理包括至少一个低k​​电介质材料破坏过程。 第二种处理恢复了低k电介质层。 优选地，第一和第二处理中的每一个包括选自电子束固化，紫外线固化，等离子体固化，SCCO 2清洁及其组合的固化过程。

公开(公告)号：US20070020952A1

公开(公告)日：2007-01-25

申请号：US11184589

申请日：2005-07-19

申请人： Keng-Chu Lin ,  Chen-Hua Yu ,  Ching-Ya Wang ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Cheng

发明人： Keng-Chu Lin ,  Chen-Hua Yu ,  Ching-Ya Wang ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Cheng

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02211 ,  H01L21/0206 ,  H01L21/02074 ,  H01L21/02101 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02334 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76834

摘要： A method of forming a low-k dielectric layer and forming a structure in the low-k dielectric layer includes depositing a low-k dielectric layer over a substrate, performing a first treatment to the low-k dielectric layer, performing post-formation processes, and performing a second treatment to the low-k dielectric layer. The k value of the low-k dielectric layer is lowered by the first treatment. The post-formation processes performed to the low-k dielectric layer include at least one low-k dielectric material damaging process. The second treatment restores the low-k dielectric layer. Preferably, each of the first and second treatments includes a curing process selected from e-beam curing, ultraviolet curing, plasma curing, SCCO2 cleaning, and combinations thereof.

摘要翻译： 形成低k电介质层并在低k电介质层中形成结构的方法包括在衬底上沉积低k电介质层，对低k电介质层进行第一次处理，执行后形成工艺 ，并对低k电介质层进行第二处理。 通过第一次处理，低k电介质层的k值降低。 对低k电介质层进行的后期处理包括至少一个低k​​电介质材料破坏过程。 第二种处理恢复了低k电介质层。 优选地，第一和第二处理中的每一个包括选自电子束固化，紫外线固化，等离子体固化，SCCO 2清洁及其组合的固化过程。

公开(公告)号：US20070161230A1

公开(公告)日：2007-07-12

申请号：US11328596

申请日：2006-01-10

申请人： I-I Chen ,  Tien-I Bao ,  Shwang-Ming Cheng ,  Chen-Hua Yu

发明人： I-I Chen ,  Tien-I Bao ,  Shwang-Ming Cheng ,  Chen-Hua Yu

IPC分类号： H01L21/4763 ,  H01L21/469

CPC分类号： H01L21/76826 ,  H01L21/7682 ,  H01L21/76825 ,  H01L2221/1047

摘要： A method of manufacturing a semiconductor device having a low-k dielectric layer is provided. An embodiment comprises forming a dielectric layer on a substrate, wherein the layer comprises a pore generating material dispersed in an uncured matrix. A second step comprises forming pores in the uncured matrix by irradiating the layer with radiation having a first wavelength. After pore forming, a third step comprises cross-linking the dielectric by irradiating it at a second wavelength, the second being less than the first. In an embodiment, the irradiating wavelengths comprise ultra-violet radiation. Embodiments may further include repairing processing damage wherein the damage includes dangling bonds or silanol formation. The repairing includes annealing in a carbon-containing ambient such as C2H4, C3H6, or hexamethyldisilazane (HMDS).

摘要翻译： 提供一种制造具有低k电介质层的半导体器件的方法。 一个实施方案包括在基底上形成介电层，其中该层包含分散在未固化的基质中的孔产生材料。 第二步骤包括通过用具有第一波长的辐射照射该层来在未固化的基质中形成孔。 在成孔之后，第三步骤包括通过以第二波长照射电介质来交联电介质，第二步小于第一波长。 在一个实施例中，照射波长包括紫外辐射。 实施方案可以进一步包括修复处理损伤，其中损伤包括悬挂键或硅烷醇形成。 修复包括在含碳环境中退火，例如C 2 H 4 H 3，C 3 H 6， 或六甲基二硅氮烷（HMDS）。

公开(公告)号：US20110217840A1

公开(公告)日：2011-09-08

申请号：US13107549

申请日：2011-05-13

申请人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

发明人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon.

摘要翻译： 一种用于制造集成电路的方法包括在半导体衬底上形成低k电介质层，蚀刻低k电介质层以形成开口，并且用气体有机化学品处理低k电介质层以引起第 低k电介质层和气态有机化学品。 气态有机化学物质不含硅。

公开(公告)号：US20080096380A1

公开(公告)日：2008-04-24

申请号：US11585610

申请日：2006-10-24

申请人： Chung-Chi Ko ,  Ting-Yu Shen ,  Keng-Chu Lin ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Jeng ,  Chen-Hua Yu

发明人： Chung-Chi Ko ,  Ting-Yu Shen ,  Keng-Chu Lin ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/76826

摘要： A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier layer, and filling the opening with a conductive material, wherein the conductive material is in contact with the dielectric barrier layer.

摘要翻译： 一种用于形成集成电路的方法包括在半导体衬底上形成低k电介质层，蚀刻低k电介质层以形成开口，形成至少覆盖开口侧壁的介电阻挡层，进行处理以改善 介电阻挡层的润湿能力，并用导电材料填充开口，其中导电材料与电介质阻挡层接触。

公开(公告)号：US07968451B2

公开(公告)日：2011-06-28

申请号：US12509039

申请日：2009-07-24

申请人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

发明人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

IPC分类号： H01L21/4763

CPC分类号： H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon.

摘要翻译： 一种用于制造集成电路的方法包括在半导体衬底上形成低k电介质层，蚀刻低k电介质层以形成开口，并且用气体有机化学品处理低k电介质层以引起第 低k电介质层和气态有机化学品。 气态有机化学物质不含硅。

公开(公告)号：US07723226B2

公开(公告)日：2010-05-25

申请号：US11654427

申请日：2007-01-17

申请人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

发明人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

摘要翻译： 提出了双层多孔低介电常数（低k）互连结构及其制造方法。 具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积的介电层和顶部沉积的介电层。 底层和顶层具有相同的原子组成，但是较高的介电常数值k。 底部介电层用作顶部介电层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。 制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。 固化过程在底部电介质层中留下的孔隙密度低于顶部介电层中留下的孔密度，这导致底部介电层中较高的介电常数k。

公开(公告)号：US20090286394A1

公开(公告)日：2009-11-19

申请号：US12509039

申请日：2009-07-24

申请人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

发明人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

IPC分类号： H01L21/768 ,  H01L21/306

CPC分类号： H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon.

摘要翻译： 一种用于制造集成电路的方法包括在半导体衬底上形成低k电介质层，蚀刻低k电介质层以形成开口，并且用气体有机化学品处理低k电介质层以引起第 低k电介质层和气态有机化学品。 气态有机化学物质不含硅。