公开(公告)号：US20080171431A1

公开(公告)日：2008-07-17

申请号：US11654427

申请日：2007-01-17

申请人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

发明人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

摘要翻译： 提出了双层多孔低介电常数（低k）互连结构及其制造方法。 具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积介电层和顶部沉积的介电层。 底层和顶层具有相同的原子组成，但是较高的介电常数值k。 底部介电层用作顶部电介质层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。 制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。 固化过程在底部电介质层中留下比在顶部电介质层中留下的孔密度更低的孔密度，这导致底部电介质层中较高的介电值k。

公开(公告)号：US07723226B2

公开(公告)日：2010-05-25

申请号：US11654427

申请日：2007-01-17

申请人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

发明人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

摘要翻译： 提出了双层多孔低介电常数（低k）互连结构及其制造方法。 具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积的介电层和顶部沉积的介电层。 底层和顶层具有相同的原子组成，但是较高的介电常数值k。 底部介电层用作顶部介电层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。 制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。 固化过程在底部电介质层中留下的孔隙密度低于顶部介电层中留下的孔密度，这导致底部介电层中较高的介电常数k。

公开(公告)号：US20080096380A1

公开(公告)日：2008-04-24

申请号：US11585610

申请日：2006-10-24

申请人： Chung-Chi Ko ,  Ting-Yu Shen ,  Keng-Chu Lin ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Jeng ,  Chen-Hua Yu

发明人： Chung-Chi Ko ,  Ting-Yu Shen ,  Keng-Chu Lin ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/76826

摘要： A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier layer, and filling the opening with a conductive material, wherein the conductive material is in contact with the dielectric barrier layer.

摘要翻译： 一种用于形成集成电路的方法包括在半导体衬底上形成低k电介质层，蚀刻低k电介质层以形成开口，形成至少覆盖开口侧壁的介电阻挡层，进行处理以改善 介电阻挡层的润湿能力，并用导电材料填充开口，其中导电材料与电介质阻挡层接触。

公开(公告)号：US09087877B2

公开(公告)日：2015-07-21

申请号：US11585610

申请日：2006-10-24

申请人： Chung-Chi Ko ,  Ting-Yu Shen ,  Keng-Chu Lin ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Jeng ,  Chen-Hua Yu

发明人： Chung-Chi Ko ,  Ting-Yu Shen ,  Keng-Chu Lin ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76831 ,  H01L21/76826

摘要： A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier layer, and filling the opening with a conductive material, wherein the conductive material is in contact with the dielectric barrier layer.

摘要翻译： 一种用于形成集成电路的方法包括在半导体衬底上形成低k电介质层，蚀刻低k电介质层以形成开口，形成至少覆盖开口侧壁的介电阻挡层，进行处理以改善 介电阻挡层的润湿能力，并用导电材料填充开口，其中导电材料与电介质阻挡层接触。

公开(公告)号：US20090258487A1

公开(公告)日：2009-10-15

申请号：US12102695

申请日：2008-04-14

申请人： Keng-Chu Lin ,  Chia-Cheng Chou ,  Chung-Chi Ko ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Shwang-Ming Jeng

发明人： Keng-Chu Lin ,  Chia-Cheng Chou ,  Chung-Chi Ko ,  Ching-Hua Hsieh ,  Cheng-Lin Huang ,  Shwang-Ming Jeng

IPC分类号： H01L21/4763

CPC分类号： H01L21/76825 ,  H01L21/3105

摘要： A method for forming an integrated circuit structure includes providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; generating hydrogen radicals using a remote plasma method; performing a first hydrogen radical treatment to the low-k dielectric layer using the hydrogen radicals; forming an opening in the low-k dielectric layer; filling the opening with a conductive material; and performing a planarization to remove excess conductive material on the low-k dielectric layer.

摘要翻译： 一种用于形成集成电路结构的方法包括提供半导体衬底; 在半导体衬底上形成低k电介质层; 使用远程等离子体法产生氢自由基; 使用氢自由基对低k电介质层进行第一次氢自由基处理; 在低k电介质层中形成开口; 用导电材料填充开口; 并执行平面化以去除低k电介质层上的过量导电材料。

公开(公告)号：US07485949B2

公开(公告)日：2009-02-03

申请号：US11797310

申请日：2007-05-02

申请人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Zhen-Cheng Wu ,  Keng-Chu Lin ,  Shwang-Ming Jeng

发明人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Zhen-Cheng Wu ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC分类号： H01L23/58

CPC分类号： H01L23/53295 ,  H01L21/563 ,  H01L21/7682 ,  H01L21/76825 ,  H01L23/5329 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079

摘要： A semiconductor device is disclosed. The device includes a substrate, a first porous SiCOH dielectric layer, a second porous SiCOH dielectric layer, and an oxide layer. The first porous SiCOH dielectric layer overlies the substrate. The second porous SiCOH dielectric layer overlies the first porous SiCOH dielectric layer. The oxide layer overlies the second porous SiCOH dielectric layer. The atomic percentage of carbon in the second porous SiCOH dielectric layer is between 16% and 22% of that in the first porous SiCOH dielectric layer.

摘要翻译： 公开了一种半导体器件。 该器件包括衬底，第一多孔SiCOH电介质层，第二多孔SiCOH电介质层和氧化物层。 第一多孔SiCOH介电层覆盖在基底上。 第二多孔SiCOH介电层覆盖第一多孔SiCOH介电层。 氧化物层覆盖第二多孔SiCOH介电层。 第二多孔SiCOH介电层中的碳的原子百分比在第一多孔SiCOH介电层中的原子百分比为16％至22％。

公开(公告)号：US08481412B2

公开(公告)日：2013-07-09

申请号：US12893399

申请日：2010-09-29

申请人： Chung-Chi Ko ,  Chia Cheng Chou ,  Keng-Chu Lin ,  Joung-Wei Liou ,  Shwang-Ming Jeng ,  Mei-Ling Chen

发明人： Chung-Chi Ko ,  Chia Cheng Chou ,  Keng-Chu Lin ,  Joung-Wei Liou ,  Shwang-Ming Jeng ,  Mei-Ling Chen

IPC分类号： H01L21/425

CPC分类号： H01L21/768 ,  H01L21/02126 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/70 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76828

摘要： A method of and apparatus for forming interconnects on a substrate includes etching patterns in ultra-low k dielectric and removing moisture from the ultra-low k dielectric using active energy assist baking. During active energy assist baking, the ultra-low k dielectric is heated and exposed to light having only wavelengths greater than 400 nm for about 1 to about 20 minutes at a temperature of about 300 to about 400 degrees Celsius. The active energy assist baking is performed after wet-cleaning or after chemical mechanical polishing, or both.

摘要翻译： 用于在衬底上形成互连的方法和装置包括在超低k电介质中的蚀刻图案，并且使用主动能量辅助烘烤从超低k电介质去除湿气。 在活性能量辅助烘烤期间，在约300至约400摄氏度的温度下，超低k电介质被加热并暴露于仅具有大于400nm波长的光约1至约20分钟。 活性能量辅助烘烤在湿清洗或化学机械抛光之后进行，或两者都进行。

公开(公告)号：US20130052755A1

公开(公告)日：2013-02-28

申请号：US13219317

申请日：2011-08-26

申请人： Chia-Cheng Chou ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

发明人： Chia-Cheng Chou ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC分类号： H01L21/66

CPC分类号： H01L22/26 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76883 ,  H01L22/12 ,  H01L22/20

摘要： A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.

公开(公告)号：US10312107B2

公开(公告)日：2019-06-04

申请号：US13228011

申请日：2011-09-08

申请人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Shing-Chyang Pan ,  Keng-Chu Lin ,  Shwang-Ming Jeng

发明人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Shing-Chyang Pan ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC分类号： H01L21/311 ,  H01L21/321 ,  H01L21/768

摘要： A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask.

公开(公告)号：US09196551B2

公开(公告)日：2015-11-24

申请号：US13219317

申请日：2011-08-26

申请人： Chia-Cheng Chou ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

发明人： Chia-Cheng Chou ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC分类号： H01L21/00 ,  H01L21/66 ,  H01L21/3105 ,  H01L21/768

CPC分类号： H01L22/26 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76883 ,  H01L22/12 ,  H01L22/20

摘要： A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.

摘要翻译： 一种方法包括蚀刻晶片上的低k电介质层以在低k电介质层中形成开口。 测量晶片中有害物质的量以获得测量结果。 响应于测量结果确定用于烘烤晶片的工艺条件。 使用确定的工艺条件烘烤晶片。