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1.发明授权Test key and method for validating the doping concentration of buried layers within a deep trench capacitors 有权用于验证深沟槽电容器内掩埋层的掺杂浓度的测试键和方法公开(公告)号：US06812487B1
公开(公告)日：2004-11-02
申请号：US10601417
申请日：2003-06-23
申请人： Tie-Jiang Wu , Chien-Chang Huang , Yu-Wei Ting , Bo-Ching Jiang , Tse-Main Kuo
发明人： Tie-Jiang Wu , Chien-Chang Huang , Yu-Wei Ting , Bo-Ching Jiang , Tse-Main Kuo
IPC分类号： H01L2358
CPC分类号： H01L27/10861 , G11C11/401 , G11C29/50 , G11C2029/0403 , G11C2029/5002 , H01L22/34 , H01L29/66181
摘要： A test key for validating the doping concentration of buried layers within a deep trench capacitor. The test key is deposited in the scribe line region of a wafer. In the test key of the present invention, the deep trench capacitor is deposited in the scribe line region and has three buried layers of three doping concentrations. An isolation region is deposited in the capacitor, and a first plug, a second and a third plug are coupled to three positions of one buried layer of the three respectively. The present invention determines whether the doping concentration of buried layers within a deep trench capacitor is valid by a first resistance measured between the first plug and the second plug and a second resistance measured between the second plug and the third plug.
摘要翻译： 一种用于验证深沟槽电容器内埋层掺杂浓度的测试键。 测试键被沉积在晶片的划线区域中。 在本发明的测试键中，深沟槽电容器沉积在划线区域中并且具有三个掺杂浓度的三个掩埋层。 隔离区域沉积在电容器中，并且第一插头，第二和第三插头分别耦合到三个一个埋层的三个位置。 本发明通过在第一插头和第二插头之间测量的第一电阻以及在第二插头和第三插头之间测量的第二电阻来确定深沟槽电容器内的埋层的掺杂浓度是否有效。
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公开(公告)号：US20060128041A1
公开(公告)日：2006-06-15
申请号：US11339687
申请日：2006-01-26
IPC分类号： H01L21/66
CPC分类号： G03F9/7088 , G03F7/70633 , G03F7/70658 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.
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公开(公告)号：US07015050B2
公开(公告)日：2006-03-21
申请号：US10718612
申请日：2003-11-24
IPC分类号： H01L21/00
CPC分类号： G03F9/7088 , G03F7/70633 , G03F7/70658 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.
摘要翻译： 提供了用于确定在集成电路制造工艺中发生的不对准的测试结构和测试方法。 测试结构包括具有第一测试结构和第二测试结构的第一导电层，其上的电介质层和介电层上的第二导电层。 第二导电层包括在第一方向和第二方向上分别与第一测试结构和第二测试结构的一部分重叠的第三测试结构和第四测试结构。 第一方向与第二方向相反。 该方法包括测量第一和第二导电层之间的电特性以计算由不对准引起的偏移量的步骤。
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4.发明授权Method and device for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal 有权用于检测DRAM装置中位线接触和有源区的对准是否正常的方法和装置公开(公告)号：US06844207B2
公开(公告)日：2005-01-18
申请号：US10452179
申请日：2003-06-02
CPC分类号： G11C29/50008 , G11C11/401 , G11C29/02 , G11C29/025
摘要： Method for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal, and a test device thereof. In the present invention a plurality of memory cells are formed in the memory area and at least one test device is formed in the scribe line region simultaneously. A first resistance and a second resistance are detected by the test device. Normal alignment of the bit line and the bar-type active area of the test device is determined according to the first resistance and the second resistance. Finally, whether the alignment of the bit line contacts and the active areas in memory areas is normal is determined according to whether the alignment of the bit line contact and bar-type active area of the test device is normal.
摘要翻译： 用于检测DRAM装置中位线接触和有源区的对准是否正常的方法及其测试装置。 在本发明中，在存储区域中形成多个存储单元，同时在划线区域中形成至少一个测试装置。 第一电阻和第二电阻由测试装置检测。 根据第一电阻和第二电阻确定测试装置的位线和条形有源区域的正常对准。 最后，根据测试装置的位线接触和条形有源区域的对准是否正常来确定位线触点的对齐和存储区域中的有效区域是否正常。
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5.发明授权Test key and method for validating the position of a word line overlaying a trench capacitor in DRAMS 有权用于验证DRAMS中覆盖沟槽电容的字线位置的测试键和方法公开(公告)号：US06825053B2
公开(公告)日：2004-11-30
申请号：US10601386
申请日：2003-06-23
申请人： Tie Jiang Wu , Chien-Chang Huang , Yu-Wei Ting , Bo Ching Jiang
发明人： Tie Jiang Wu , Chien-Chang Huang , Yu-Wei Ting , Bo Ching Jiang
IPC分类号： H01L2166
CPC分类号： H01L27/10861 , G11C8/14 , H01L22/34 , H01L27/0207 , H01L27/1087 , H01L27/10891
摘要： A test key for validating the position of a word line structure overlaying a deep trench capacitor of a DRAM. The test key is deposited in the scribe line region of a wafer. The deep trench capacitor is deposited in the scribe line region and has a buried plate. A rectangular word line is deposited in the scribe line and covers a portion of the deep trench capacitor, and two passing word lines are deposited above the deep trench. A first doping region and a second doping region are deposited between the rectangular word line and the first passing word line and between the rectangular word line and the second passing word line respectively. A first plug, a second plug and a third plugs are coupled to the first doping region, the second doping region and the buried plate respectively.
摘要翻译： 用于验证覆盖DRAM的深沟槽电容器的字线结构的位置的测试键。 测试键被沉积在晶片的划线区域中。 深沟槽电容器沉积在划线区域并具有掩埋板。 在划线中沉积矩形字线并覆盖深沟槽电容器的一部分，并且在深沟槽上方沉积两条经过的字线。 第一掺杂区域和第二掺杂区域分别沉积在矩形字线和第一通过字线之间以及矩形字线和第二通过字线之间。 第一插头，第二插头和第三插头分别耦合到第一掺杂区域，第二掺杂区域和掩埋板。
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6.发明授权Device and method for detecting alignment of active areas and memory cell structures in DRAM devices 有权用于检测DRAM器件中的有源区和存储单元结构的对准的装置和方法公开(公告)号：US07026647B2
公开(公告)日：2006-04-11
申请号：US10673310
申请日：2003-09-29
IPC分类号： H01L23/58
CPC分类号： H01L27/10876 , G11C11/401 , G11C29/36 , G11C2029/5002 , H01L22/34 , H01L27/10841
摘要： A test device and method for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors. In the test device, parallel first and second memory cell structures disposed in the scribe line region, each has a deep trench capacitor and a transistor structure. An active area is disposed between the first and second memory cell structures. The active area overlaps the first and second memory cell structures by a predetermined width. First and second conductive pads are disposed on both ends of the first memory cell structures respectively, and third and fourth conductive pads are disposed on both ends of the first memory cell structures respectively.
摘要翻译： 一种用于检测具有垂直晶体管的DRAM器件中的有源区和存储单元结构的对准的测试装置和方法。 在测试装置中，设置在划线区域中的并行第一和第二存储单元结构各自具有深沟槽电容器和晶体管结构。 有源区域设置在第一和第二存储单元结构之间。 活动区域与第一和第二存储单元结构重叠预定宽度。 第一和第二导电焊盘分别设置在第一存储单元结构的两端，第三和第四导电焊盘分别设置在第一存储单元结构的两端。
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公开(公告)号：US06891216B1
公开(公告)日：2005-05-10
申请号：US10664163
申请日：2003-09-17
IPC分类号： H01L21/334 , H01L21/8242 , H01L23/544 , H01L27/108 , H01L31/119 , H01L29/76 , H01L29/94
CPC分类号： H01L22/34 , H01L27/10829 , H01L27/10861 , H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L29/66181
摘要： A test structure of a DRAM array includes a substrate. A transistor is formed on the substrate and has a first region and a second region as source/drain regions thereof. A deep trench capacitor is formed adjacent to the transistor and has a first width. A shallow trench isolation is formed in a top portion of the deep trench capacitor and has a second width. The second width is substantially shorter than the first one. A third region is formed adjacent to the deep trench capacitor. A first contact is formed on the substrate and contacts with the first region. A second contact is formed on the substrate and contacts with the third region.
摘要翻译： DRAM阵列的测试结构包括基板。 晶体管形成在衬底上并且具有第一区域和第二区域作为其源极/漏极区域。 深沟槽电容器形成在与晶体管相邻并且具有第一宽度。 浅沟槽隔离形成在深沟槽电容器的顶部，并且具有第二宽度。 第二宽度基本上比第一宽度短。 第三区域形成为与深沟槽电容器相邻。 第一触点形成在基板上并与第一区域接触。 第二触点形成在基板上并与第三区域接触。
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8.发明授权Device and method for detecting alignment of bit lines and bit line contacts in DRAM devices 有权用于检测DRAM器件中位线和位线触点的对准的装置和方法公开(公告)号：US06693834B1
公开(公告)日：2004-02-17
申请号：US10448727
申请日：2003-05-29
申请人： Tie Jiang Wu , Chien-Chang Huang , Yu-Wei Ting , Bo Ching Jiang
发明人： Tie Jiang Wu , Chien-Chang Huang , Yu-Wei Ting , Bo Ching Jiang
IPC分类号： G11C700
CPC分类号： H01L27/10829 , G03F7/70633 , G03F7/70658 , G11C11/401 , G11C29/02 , G11C29/025 , H01L22/34 , H01L27/0207 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897
摘要： A method and device for detecting alignment of bit lines and bit line contacts in DRAM devices. In the present invention, the test device is disposed in the scribe line region and is formed by the same masks and process as the bit lines and bit line contacts in the memory regions simultaneously. The memory deices and test may have the same alignment shift between bit line contacts and bit line due to use of the same masks and process. Thus, alignment of bit lines and bit line contacts in the memory region is determined according to two resistances (R1 and R2) detected by the test device. Further, the alignment shift can be obtained by Δ W = R MO × L × ( 1 R 1 - 1 R 2 ) , wherein RMO is the resistance per surface area of the bit lines, and L is the length of the bar-type bit line contacts in the test device.
摘要翻译： 一种用于检测DRAM器件中位线和位线触点的对准的方法和装置。 在本发明中，测试装置设置在划线区域中，并且与存储区域中的位线和位线接触同样的掩模和处理形成。 由于使用相同的掩模和过程，存储器和测试可能在位线触点和位线之间具有相同的对准位移。 因此，根据由测试装置检测到的两个电阻（R1和R2）来确定存储器区域中位线和位线触点的对准。 此外，通过其中RMO是位线的每个表面积的电阻，并且L是测试装置中条形位线触点的长度，可以获得对准偏移。
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9.发明授权Device and method for detecting alignment of active areas and memory cell structures in DRAM devices 有权用于检测DRAM器件中的有源区和存储单元结构的对准的装置和方法公开(公告)号：US07381575B2
公开(公告)日：2008-06-03
申请号：US11096836
申请日：2005-03-30
IPC分类号： H01L21/66
CPC分类号： H01L27/10876 , G11C11/401 , G11C29/36 , G11C2029/5002 , H01L22/34 , H01L27/10841
摘要： A test device and method for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors. In the test device, parallel first and second memory cell structures disposed in the scribe line region, each has a deep trench capacitor and a transistor structure. An active area is disposed between the first and second memory cell structures. The active area overlaps the first and second memory cell structures by a predetermined width. First and second conductive pads are disposed on both ends of the first memory cell structures respectively, and third and fourth conductive pads are disposed on both ends of the first memory cell structures respectively.
摘要翻译： 一种用于检测具有垂直晶体管的DRAM器件中的有源区和存储单元结构的对准的测试装置和方法。 在测试装置中，设置在划线区域中的并行第一和第二存储单元结构各自具有深沟槽电容器和晶体管结构。 有源区域设置在第一和第二存储单元结构之间。 活动区域与第一和第二存储单元结构重叠预定宽度。 第一和第二导电焊盘分别设置在第一存储单元结构的两端，第三和第四导电焊盘分别设置在第一存储单元结构的两端。
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10.发明授权Method and device for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal 有权用于检测DRAM装置中位线接触和有源区的对准是否正常的方法和装置公开(公告)号：US06984534B2
公开(公告)日：2006-01-10
申请号：US10809999
申请日：2004-03-26
IPC分类号： G01R31/26
CPC分类号： G11C29/50008 , G11C11/401 , G11C29/02 , G11C29/025
摘要： Method for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal, and a test device thereof. In the present invention a plurality of memory cells are formed in the memory area and at least one test device is formed in the scribe line region simultaneously. A first resistance and a second resistance are detected by the test device. Normal alignment of the bit line and the bar-type active area of the test device is determined according to the first resistance and the second resistance. Finally, whether the alignment of the bit line contacts and the active areas in memory areas is normal is determined according to whether the alignment of the bit line contact and bar-type active area of the test device is normal.
摘要翻译： 用于检测DRAM装置中位线接触和有源区的对准是否正常的方法及其测试装置。 在本发明中，在存储区域中形成多个存储单元，同时在划线区域中形成至少一个测试装置。 第一电阻和第二电阻由测试装置检测。 根据第一电阻和第二电阻确定测试装置的位线和条形有源区域的正常对准。 最后，根据测试装置的位线接触和条形有源区域的对准是否正常来确定位线触点的对齐和存储区域中的有效区域是否正常。
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