公开(公告)号：US06417046B1

公开(公告)日：2002-07-09

申请号：US09563834

申请日：2000-05-05

申请人： Ming-Chou Ho ,  Wen-Ting Chu ,  Chang Song Lin ,  Chuan-Li Chang ,  Hsin-Ming Chen ,  Di-Son Kuo

发明人： Ming-Chou Ho ,  Wen-Ting Chu ,  Chang Song Lin ,  Chuan-Li Chang ,  Hsin-Ming Chen ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L21/28211 ,  H01L21/28247 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/511 ,  H01L29/6659

摘要： A modified nitride spacer and making of the same are disclosed. The modified nitride spacer is formed adjacent a high-temperature oxide (HTO) layer which in turn is formed adjacent the sidewalls of a gate electrode. It is shown that the placement of an intervening oxide layer between the sidewalls of the gate electrode and the nitride spacer, in that order only, provides a significant improvement in charge retention in floating gate memory cells. Also, forming of the spacer from pure, undoped oxide only yields the same favorable results.

公开(公告)号：US6117732A

公开(公告)日：2000-09-12

申请号：US193671

申请日：1998-11-17

申请人： Wen-Ting Chu ,  Chuan-Li Chang ,  Ming-Chou Ho ,  Chang-Song Lin ,  Di-Son Kuo

发明人： Wen-Ting Chu ,  Chuan-Li Chang ,  Ming-Chou Ho ,  Chang-Song Lin ,  Di-Son Kuo

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A method for fabricating a single polysilicon, non-volatile memory device, has been developed. The method features the use of a metal structure, comprised to contact an underlying control gate region, located in the semiconductor structure, in addition to providing the upper electrode, for a capacitor structure. The capacitor structure, in addition to the metal structure used as the upper electrode, is also comprised of an underlying capacitor dielectric layer, and an underlying polysilicon floating gate structure, used as the lower electrode of the capacitor structure. The creation of the capacitor structure results in performance increases realized via the additional control gate coupling capacitance, obtained via the novel configuration described in this invention.

摘要翻译： 已经开发了用于制造单个多晶硅，非易失性存储器件的方法。 该方法的特征在于，除了为电容器结构提供上电极之外，金属结构的使用还包括接触位于半导体结构中的底层控制栅极区域。 除了用作上电极的金属结构之外，电容器结构还包括用作电容器结构的下电极的下层电容器介电层和下面的多晶硅浮栅结构。 电容器结构的产生导致通过经由本发明中描述的新颖结构获得的附加控制栅极耦合电容实现的性能提高。

公开(公告)号：US06403494B1

公开(公告)日：2002-06-11

申请号：US09638300

申请日：2000-08-14

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Jack Yeh ,  Chia-Ta Hsieh ,  Chuan-Li Chang

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Jack Yeh ,  Chia-Ta Hsieh ,  Chuan-Li Chang

IPC分类号： H01L2100

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to a shallow trench isolation (STI), which in turn makes it self-aligned to source and to word line. This will advantageously affect a shrinkage in the size of the memory cell. In a first embodiment, the close self-alignment is made possible through a new use of an anti-reflective coating (ARC) in the various process steps of the making of the cell. In the second embodiment, a low-viscosity material is used in such a manner so as to enable self-alignment of the floating gate to the STI in a simple way.

摘要翻译： 公开了一种用于形成分裂栅极闪存单元的方法，其中单元的浮置栅极自对准到浅沟槽隔离（STI），其又使得其自对准到源极和字线。 这将有利地影响存储器单元的尺寸的收缩。 在第一实施例中，通过在制造电池的各种工艺步骤中新的使用抗反射涂层（ARC）使得紧密的自对准成为可能。 在第二实施例中，以这样的方式使用低粘度材料，以便能够以简单的方式使浮动栅极与STI的自对准。

公开(公告)号：US06468863B2

公开(公告)日：2002-10-22

申请号：US09761276

申请日：2001-01-16

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jake Yeh ,  Chuan-Li Chang ,  Wen-Ting Chu ,  Sheng-Wei Tsaur

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jake Yeh ,  Chuan-Li Chang ,  Wen-Ting Chu ,  Sheng-Wei Tsaur

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： Within both a method for fabricating a split gate field effect transistor and the split gate field effect transistor fabricated employing the method, there is employed a patterned silicon nitride barrier dielectric layer formed covering a first portion of a floating gate and a first portion of a semiconductor substrate adjacent the first portion of the floating gate. Within the first portion of the semiconductor substrate there is eventually formed a source/drain region, and more particularly a source region, when fabricating the split gate field effect transistor. The patterned silicon nitride barrier dielectric layer inhibits when fabricating the split gate field effect transistor ion implant damage of the floating gate and oxidative loss of a floating gate electrode edge.

摘要翻译： 在制造分裂栅极场效应晶体管的方法和使用该方法制造的分裂栅极场效应晶体管的两者中，采用形成为覆盖浮置栅极的第一部分和半导体的第一部分的图案化氮化硅阻挡介电层 衬底邻近浮动栅极的第一部分。 在半导体衬底的第一部分内，当制造分裂栅极场效应晶体管时，最终形成源极/漏极区域，尤其是源极区域。 图案化的氮化硅阻挡介电层在制造分离栅场效应晶体管离子注入损坏浮栅和浮栅电极边缘的氧化损失时禁止。

公开(公告)号：US06387757B1

公开(公告)日：2002-05-14

申请号：US09761912

申请日：2001-01-17

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Jake Yeh ,  Chia-Da Hsieh ,  Chuan-Li Chang ,  Sheng-Wei Tsaur

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Jake Yeh ,  Chia-Da Hsieh ,  Chuan-Li Chang ,  Sheng-Wei Tsaur

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： Within a method for fabricating a split gate field effect transistor (FET) within a semiconductor integrated circuit microelectronic fabrication, there is employed a sacrificial self aligned spacer layer which defines a control gate electrode channel within the split gate field effect transistor (FET). The sacrificial self aligned spacer layer is employed as part of an ion implantation mask employed for forming a source/drain region adjoining the control gate electrode channel within the split gate field effect transistor (FET). The sacrificial self aligned spacer layer is stripped from over the control gate electrode channel prior to forming over the control gate electrode channel a control gate electrode within the split gate field effect transistor.

摘要翻译： 在用于在半导体集成电路微电子制造中制造分裂栅极场效应晶体管（FET）的方法中，采用限定分裂栅极场效应晶体管（FET）内的控制栅电极通道的牺牲自对准间隔层。 牺牲自对准间隔层被用作用于形成与分离栅场效应晶体管（FET）内的控制栅电极通道相邻的源/漏区的离子注入掩模的一部分。 在控制栅电极通道上形成分割栅场效应晶体管内的控制栅极电极之前，将牺牲自对准间隔层从控制栅电极通道上剥离。

公开(公告)号：US06538277B2

公开(公告)日：2003-03-25

申请号：US09920601

申请日：2001-08-02

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chuang-Ke Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin ,  Wen-Ting Chu

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chuang-Ke Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin ,  Wen-Ting Chu

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825

摘要： A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.

摘要翻译： 公开了一种形成分裂栅闪存单元中用于增强的F-N隧穿的第一多晶硅栅尖（多尖端）的新方法。 在不使用厚多晶硅层作为浮动栅极的情况下形成多尖端。 这可以通过在多晶硅上形成氧化层并氧化多晶硅的侧壁来实现。 由于浮栅的多晶硅的起始厚度相对较薄，所以形成的栅极尖或多尖端也必然是薄且尖锐的。 因此，该方法避免了超大规模集成技术的缩小设备中遇到的氧化物薄化问题，提高了EEPROM的快速可编程性和擦除性能。

公开(公告)号：US06534821B2

公开(公告)日：2003-03-18

申请号：US09927071

申请日：2001-08-10

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-ke Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-ke Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide. The vertical wall of the protruding structure over the source is used to form vertical floating gate and spacer control gate with an intervening inter-gate oxide. Because the coupling between the source and the floating gate is now provided through the vertical wall, the coupling area is much larger than with conventional flat source. Furthermore, there is no longer the problem of voltage punch-through between the source and the drain. The vertical floating gate is also made thin so that the resulting thin and sharp poly-tip enhances further the erasing and programming speed of the flash memory cell. The vertical orientation of the source structure and the floating gate and the self-alignment of the spacer control gate to the floating gate together makes it possible to reduce the memory cell substantially.

公开(公告)号：US06333228B1

公开(公告)日：2001-12-25

申请号：US09534160

申请日：2000-03-24

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Jack Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method is provided to improve the control of bird's beak profile of poly in a split gate flash memory cell. The control of the bird's beak profile is achieved in a first embodiment where the polycrystalline layer of the floating gate is annealed at a high temperature. The annealing promotes small grain size and hence smoother surface in the polysilicon, which in turn promotes sharper poly tip. The smoother poly surface also results in thinner inter-poly between the floating gate and the control gate, which together with the sharp poly tip, enhances the erase speed of the split-gate flash memory cell. In a second embodiment, the performance is further enhanced by providing an amorphous silicon for the floating gate, because the amorphous nature of the silicon yields a very smooth surface. This smooth surface is transferred to the recrystallized state of the silicon layer through annealing. Thus, a good control for the bird's beak is achieved. A sharp and short poly tip then results from a well controlled and well-defined bird's beak. Hence, an enhanced split-gate flash memory cell follows.

摘要翻译： 提供了一种方法来改善分裂门闪存单元中聚鸟的鸟嘴形状的控制。 在第一实施例中实现鸟嘴形状的控制，其中浮栅的多晶层在高温下退火。 退火促进了多晶硅中的小晶粒尺寸和因此更平滑的表面，这又促进了更尖锐的多晶硅尖端。 更平滑的多晶面也导致浮栅和控制栅之间的更薄的多晶硅，其与尖锐的多晶硅尖端一起增强了分离栅闪存单元的擦除速度。 在第二实施例中，通过为浮置栅极提供非晶硅来进一步提高性能，因为硅的无定形性能产生非常光滑的表面。 该光滑表面通过退火转移到硅层的再结晶状态。 因此，可以很好地控制鸟的喙。 然后，一个尖锐和短的多头尖端来自良好控制和明确定义的鸟的喙。 因此，增强的分闸式闪存单元如下。

公开(公告)号：US06312989B1

公开(公告)日：2001-11-06

申请号：US09489496

申请日：2000-01-21

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide. The vertical wall of the protruding structure over the source is used to form vertical floating gate and spacer control gate with an intervening inter-gate oxide. Because the coupling between the source and the floating gate is now provided through the vertical wall, the coupling area is much larger than with conventional flat source. Furthermore, there is no longer the problem of voltage punch-through between the source and the drain. The vertical floating gate is also made thin so that the resulting thin and sharp poly-tip enhances further the erasing and programming speed of the flash memory cell. The vertical orientation of the source structure and the floating gate and the self-alignment of the spacer control gate to the floating gate together makes it possible to reduce the memory cell substantially.

摘要翻译： 公开了一种用于形成具有突出源的分裂栅极闪存单元来代替常规扁平源的方法。 垂直突出的源结构具有顶部和底部。 底部是多晶硅，而顶部是多晶氧化物。 源极上的突出结构的垂直壁用于形成具有中间栅极氧化物的垂直浮动栅极和间隔物控制栅极。 因为现在通过垂直壁提供源极和浮动栅极之间的耦合，所以耦合面积比常规扁平源大得多。 此外，不再存在源极和漏极之间的电压穿通的问题。 垂直浮动栅极也变薄，使得所得到的薄而尖锐的多尖端进一步增强了闪存单元的擦除和编程速度。 源结构和浮置栅极的垂直取向以及间隔物控制栅极与浮置栅极的自对准一起使得可以基本上减小存储单元。

公开(公告)号：US06251744B1

公开(公告)日：2001-06-26

申请号：US09356870

申请日：1999-07-19

申请人： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Wen-Ting Chu ,  Hung-Cheng Sung ,  Di-Son Kuo

发明人： Hung-Der Su ,  Chrong-Jung Lin ,  Jong Chen ,  Wen-Ting Chu ,  Hung-Cheng Sung ,  Di-Son Kuo

IPC分类号： H01L2176

CPC分类号： H01L21/76213

摘要： A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is created in the high voltage device region. A layer of sacrificial oxide is deposited on the surface of the semiconductor substrate. A low voltage cluster n-well implant is performed in the high voltage PMOS region of the semiconductor substrate followed, for the high voltage NMOS region, by a low voltage cluster p-well implant which is followed by a buried p-well cluster implant.

摘要翻译： 在半导体衬底的n阱或p阱区域上生长一层良好的氧化物。 在高电压器件区域中进行深n阱注入，随后是深n阱注入的深n阱驱动。 去除氧化物; 在高电压器件区域中产生场氧化物（FOX）区域。 牺牲氧化物层沉积在半导体衬底的表面上。 在半导体衬底的高电压PMOS区域中执行低电压簇n阱注入，随后是高压NMOS区，由低电压簇p阱注入，随后是埋置的p阱簇注入。