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    Use of a metal contact structure to increase control gate coupling capacitance for a single polysilicon non-volatile memory cell
    2.
    发明授权
    Use of a metal contact structure to increase control gate coupling capacitance for a single polysilicon non-volatile memory cell 有权
    使用金属接触结构来增加单个多晶硅非易失性存储单元的控制栅极耦合电容

    公开(公告)号：US6117732A

    公开(公告)日：2000-09-12

    申请号：US193671

    申请日：1998-11-17

    申请人： Wen-Ting Chu ,  Chuan-Li Chang ,  Ming-Chou Ho ,  Chang-Song Lin ,  Di-Son Kuo

    发明人： Wen-Ting Chu ,  Chuan-Li Chang ,  Ming-Chou Ho ,  Chang-Song Lin ,  Di-Son Kuo

    IPC分类号： H01L21/336 ,  H01L21/8247

    CPC分类号： H01L29/66825

    摘要： A method for fabricating a single polysilicon, non-volatile memory device, has been developed. The method features the use of a metal structure, comprised to contact an underlying control gate region, located in the semiconductor structure, in addition to providing the upper electrode, for a capacitor structure. The capacitor structure, in addition to the metal structure used as the upper electrode, is also comprised of an underlying capacitor dielectric layer, and an underlying polysilicon floating gate structure, used as the lower electrode of the capacitor structure. The creation of the capacitor structure results in performance increases realized via the additional control gate coupling capacitance, obtained via the novel configuration described in this invention.

    摘要翻译： 已经开发了用于制造单个多晶硅，非易失性存储器件的方法。 该方法的特征在于，除了为电容器结构提供上电极之外，金属结构的使用还包括接触位于半导体结构中的底层控制栅极区域。 除了用作上电极的金属结构之外，电容器结构还包括用作电容器结构的下电极的下层电容器介电层和下面的多晶硅浮栅结构。 电容器结构的产生导致通过经由本发明中描述的新颖结构获得的附加控制栅极耦合电容实现的性能提高。

    SILICON-ON-INSULATOR (SOI) MEMORY DEVICE
    3.
    发明申请
    SILICON-ON-INSULATOR (SOI) MEMORY DEVICE 审中-公开
    绝缘体绝缘体（SOI）存储器件

    公开(公告)号：US20070296034A1

    公开(公告)日：2007-12-27

    申请号：US11759949

    申请日：2007-06-08

    申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Ming-Chou Ho ,  Shih-Jye Shen

    发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Ming-Chou Ho ,  Shih-Jye Shen

    IPC分类号： H01L27/12

    CPC分类号： H01L27/1203 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11558

    摘要： A single-poly SOI memory cell includes a PMOS select transistor serially connected with a floating-gate PMOS transistor on an SOI substrate. The PMOS select transistor includes a select gate, a P+ source region and a P+ drain/source region. The floating-gate PMOS transistor includes a floating gate, a P+ drain region and the P+ drain/source region, wherein the P+ drain/source region is shared by the PMOS select transistor and the floating-gate PMOS transistor. A floating first N+ doping region is disposed within the P+ drain/source region. The first N+ doping region, which is adjacent to the floating gate, acts as a source-tie pick-up.

    摘要翻译： 单多晶硅存储单元包括与SOI衬底上的浮栅PMOS晶体管串联连接的PMOS选择晶体管。 PMOS选择晶体管包括选择栅极，P + SUP源极区和P + SUP漏极/源极区。 浮置栅极PMOS晶体管包括浮置栅极，漏极和漏极区域，其中P + 漏极/源极区域由PMOS选择晶体管和浮置栅极PMOS晶体管共享。 漂浮的第一N + +掺杂区域设置在漏极/源极区域内。 与浮动栅极相邻的第一N + H + +掺杂区充当源极接头。

    Fabrication method for non-volatile memory
    6.
    发明授权
    Fabrication method for non-volatile memory 有权
    非易失性存储器的制作方法

    公开(公告)号：US06812083B2

    公开(公告)日：2004-11-02

    申请号：US10463610

    申请日：2003-06-18

    申请人： Shih-Jye Shen ,  Wei-Zhe Wong ,  Ming-Chou Ho ,  Hsin-Ming Chen

    发明人： Shih-Jye Shen ,  Wei-Zhe Wong ,  Ming-Chou Ho ,  Hsin-Ming Chen

    IPC分类号： H01L21336

    CPC分类号： H01L27/115 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C2216/10

    摘要： A fabrication method for a non-volatile memory includes providing a first metal oxide semiconductor (MOS) transistor having a control gate and a second MOS transistor having a source, a drain, and a floating gate. The first MOS transistor and the second MOS transistor are formed on a well. The method further includes biasing the first MOS with a first biasing voltage to actuate the first MOS transistor, biasing the second MOS transistor with a second biasing voltage to enable the second MOS transistor to generate a gate current, and adjusting capacitances between the floating gate of the second MOS transistor and the drain, the source, the control gate, and the well according to voltage difference between the floating gate of the second MOS transistor and the source of the second MOS transistor.

    摘要翻译： 用于非易失性存储器的制造方法包括提供具有控制栅极的第一金属氧化物半导体（MOS）晶体管和具有源极，漏极和浮置栅极的第二MOS晶体管。 第一MOS晶体管和第二MOS晶体管形成在阱上。 该方法还包括以第一偏置电压偏置第一MOS以致动第一MOS晶体管，以第二偏置电压偏置第二MOS晶体管，以使第二MOS晶体管产生栅极电流，并调整第二MOS晶体管的浮置栅极之间的电容 第二MOS晶体管和漏极，源极，控制栅极和阱，根据第二MOS晶体管的浮置栅极和第二MOS晶体管的源极之间的电压差。

    ONE-TIME PROGRAMMABLE READ-ONLY MEMORY
    7.
    发明申请
    ONE-TIME PROGRAMMABLE READ-ONLY MEMORY 审中-公开
    一次性可编程只读存储器

    公开(公告)号：US20100006924A1

    公开(公告)日：2010-01-14

    申请号：US12171301

    申请日：2008-07-11

    申请人： Hsin-Ming Chen ,  Shao-Chang Huang ,  Shih-Chen Wang ,  Tsung-Mu Lai ,  Ming-Chou Ho ,  Chrong-Jung Lin

    发明人： Hsin-Ming Chen ,  Shao-Chang Huang ,  Shih-Chen Wang ,  Tsung-Mu Lai ,  Ming-Chou Ho ,  Chrong-Jung Lin

    IPC分类号： H01L27/112

    CPC分类号： H01L27/112 ,  H01L27/11206 ,  H01L27/11521

    摘要： A one-time programmable read-only memory (OTP-ROM) including a substrate, a first doped region, a second doped region, a third doped region, a first dielectric layer, a select gate, a second dielectric layer, a first channel, a second channel and a silicide layer is provided. The first doped region, the second doped region and the third doped region are disposed apart in a substrate. The first dielectric layer is disposed on the substrate between the first doped region and the second doped region. The select gate is disposed on the first dielectric layer. The second dielectric layer is disposed on the substrate between the second doped region and the third doped region. The silicide layer is disposed on the first doped region, the second doped region and the third doped region. The OTP-ROM stores data by a punch-through effect occurring between the second doped region and the third doped region.

    摘要翻译： 一种包括衬底，第一掺杂区域，第二掺杂区域，第三掺杂区域，第一介电层，选择栅极，第二介电层，第一沟道 ，提供第二通道和硅化物层。 第一掺杂区域，第二掺杂区域和第三掺杂区域设置在衬底中。 第一介电层设置在第一掺杂区和第二掺杂区之间的衬底上。 选择栅极设置在第一电介质层上。 第二介电层设置在第二掺杂区和第三掺杂区之间的衬底上。 硅化物层设置在第一掺杂区域，第二掺杂区域和第三掺杂区域上。 OTP-ROM通过发生在第二掺杂区域和第三掺杂区域之间的穿透效应来存储数据。