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    Process for integration of a high dielectric constant gate insulator layer in a CMOS device
    1.
    发明授权
    Process for integration of a high dielectric constant gate insulator layer in a CMOS device 失效
    在CMOS器件中集成高介电常数栅极绝缘体层的工艺

    公开(公告)号：US06914313B2

    公开(公告)日：2005-07-05

    申请号：US10696007

    申请日：2003-10-29

    申请人： Ming-Fang Wang ,  Chien-Hao Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

    发明人： Ming-Fang Wang ,  Chien-Hao Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

    IPC分类号： H01L21/8238 ,  H01L29/76

    CPC分类号： H01L21/823857 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  Y10S257/90

    摘要： A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.

    摘要翻译： 已经开发了CMOS器件结构，以及制造具有由高k金属氧化物层构成的栅极绝缘体层的CMOS器件的方法。 在沉积高k金属氧化物层之前，该工艺特征是形成凹陷的，重掺杂的源极/漏极区域以及垂直的多晶硅LDD间隔物。 先前用作凹陷区域的掩模的氮化硅形状的去除，其又用于重掺杂源极/漏极区域的适应，提供了由高k金属氧化物层占据的空间。 通过延迟沉积金属氧化物层，在高温下进行保存，通过垂直多晶硅间隔物对接的高k栅极绝缘体层的完整性，并覆盖由半导体衬底的非凹陷部分提供的沟道区域 退火如重掺杂源极/漏极区的激活退火，以及用于金属硅化物形成的退火。

    Process for integration of a high dielectric constant gate insulator layer in a CMOS device
    4.
    发明授权
    Process for integration of a high dielectric constant gate insulator layer in a CMOS device 有权
    在CMOS器件中集成高介电常数栅极绝缘体层的工艺

    公开(公告)号：US06656764B1

    公开(公告)日：2003-12-02

    申请号：US10146287

    申请日：2002-05-15

    申请人： Ming-Fang Wang ,  Chien-Hao Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

    发明人： Ming-Fang Wang ,  Chien-Hao Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

    IPC分类号： H01L2100

    CPC分类号： H01L21/823857 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  Y10S257/90

    摘要： A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.

    摘要翻译： 已经开发了CMOS器件结构，以及制造具有由高k金属氧化物层构成的栅极绝缘体层的CMOS器件的方法。 在沉积高k金属氧化物层之前，该工艺特征是形成凹陷的，重掺杂的源极/漏极区域以及垂直的多晶硅LDD间隔物。 先前用作凹陷区域的掩模的氮化硅形状的去除，其又用于重掺杂源极/漏极区域的适应，提供了由高k金属氧化物层占据的空间。 通过延迟沉积金属氧化物层，在高温下进行保存，通过垂直多晶硅间隔物对接的高k栅极绝缘体层的完整性，并覆盖由半导体衬底的非凹陷部分提供的沟道区域 退火如重掺杂源极/漏极区的激活退火，以及用于金属硅化物形成的退火。

    Process for integration of a high dielectric constant gate insulator layer in a CMOS device
    5.
    发明授权
    Process for integration of a high dielectric constant gate insulator layer in a CMOS device 有权
    在CMOS器件中集成高介电常数栅极绝缘体层的工艺

    公开(公告)号：US07393766B2

    公开(公告)日：2008-07-01

    申请号：US11119951

    申请日：2005-05-02

    申请人： Ming-Fang Wang ,  Chien-Hao Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

    发明人： Ming-Fang Wang ,  Chien-Hao Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

    IPC分类号： H01L21/425

    CPC分类号： H01L21/823857 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  Y10S257/90

    摘要： A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.

    摘要翻译： 已经开发了CMOS器件结构，以及制造具有由高k金属氧化物层构成的栅极绝缘体层的CMOS器件的方法。 在沉积高k金属氧化物层之前，该工艺特征是形成凹陷的，重掺杂的源极/漏极区域以及垂直的多晶硅LDD间隔物。 先前用作凹陷区域的掩模的氮化硅形状的去除，其又用于重掺杂源极/漏极区域的适应，提供了由高k金属氧化物层占据的空间。 通过延迟沉积金属氧化物层，在高温下进行保存，通过垂直多晶硅间隔物对接的高k栅极绝缘体层的完整性，并覆盖由半导体衬底的非凹陷部分提供的沟道区域 退火如重掺杂源极/漏极区的激活退火，以及用于金属硅化物形成的退火。

    Noble high-k device
    7.
    发明授权
    Noble high-k device 有权
    高贵的高k设备

    公开(公告)号：US07351994B2

    公开(公告)日：2008-04-01

    申请号：US10762164

    申请日：2004-01-21

    申请人： Liang-Gi Yao ,  Tien-Chih Chang ,  Ming-Fang Wang ,  Shih-Chang Chen ,  Mong-Song Liang

    发明人： Liang-Gi Yao ,  Tien-Chih Chang ,  Ming-Fang Wang ,  Shih-Chang Chen ,  Mong-Song Liang

    IPC分类号： H01L29/06 ,  H01L21/336

    CPC分类号： H01L29/517 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054

    摘要： At least one high-k device, and a method for forming the at least one high-k device, comprising the following. A structure having a strained substrate formed thereover. The strained substrate comprising at least an uppermost strained-Si epi layer. At least one dielectric gate oxide portion over the strained substrate. The at least one dielectric gate oxide portion having a dielectric constant of greater than about 4.0. A device over each of the at least one dielectric gate oxide portion to complete the least one high-k device. A method of forming the at least one high-k device.

    摘要翻译： 至少一个高k装置和用于形成至少一个高k装置的方法包括以下。 具有在其上形成的应变衬底的结构。 应变衬底包括至少最上层的应变Si外延层。 在应变衬底上的至少一个电介质栅极氧化物部分。 所述至少一个电介质栅极氧化物部分具有大于约4.0的介电常数。 在所述至少一个电介质栅极氧化物部分中的每一个上方的器件，以完成所述至少一个高k器件。 一种形成所述至少一个高k装置的方法。

    Dual gate dielectric scheme: SiON for high performance devices and high K for low power devices
    8.
    再颁专利
    Dual gate dielectric scheme: SiON for high performance devices and high K for low power devices 有权
    双栅电介质方案：用于高性能器件的SiON和低功率器件的高K

    公开(公告)号：USRE43673E1

    公开(公告)日：2012-09-18

    申请号：US11518593

    申请日：2006-09-08

    申请人： Tou-Hung Hou ,  Ming-Fang Wang ,  Chi-Chun Chen ,  Chih-Wei Yang ,  Liang-Gi Yao ,  Shih-Chang Chen

    发明人： Tou-Hung Hou ,  Ming-Fang Wang ,  Chi-Chun Chen ,  Chih-Wei Yang ,  Liang-Gi Yao ,  Shih-Chang Chen

    IPC分类号： H01L21/8238 ,  H01L29/76

    CPC分类号： H01L21/823456 ,  H01L21/823462

    摘要： A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT

    摘要翻译： 描述了可扩展以满足对于50nm和70nm技术节点的要求的形成双栅极电介质层的方法。 衬底具有分离器件区域的STI区域。 界面层和高k电介质层依次沉积在衬底上。 在一个器件区域上去除两个层，并且在暴露的器件区域上生长具有EOT <10nm的超薄氮氧化硅层。 在SiON介电层的生长期间，高k电介质层退火。 高k电介质层由金属氧化物或其硅酸盐或铝酸盐形成，并且能够以具有抑制的漏电流的EOT <1.8nm制造低功率器件。 当形成多个栅极时，该方法与双重或三重氧化物厚度工艺兼容。

    Noble high-k device
    9.
    发明申请
    Noble high-k device 有权
    高贵的高k设备

    公开(公告)号：US20050156255A1

    公开(公告)日：2005-07-21

    申请号：US10762164

    申请日：2004-01-21

    申请人： Liang-Gi Yao ,  Tien-Chih Chang ,  Ming-Fang Wang ,  Shih-Chang Chen ,  Mong-Song Liang

    发明人： Liang-Gi Yao ,  Tien-Chih Chang ,  Ming-Fang Wang ,  Shih-Chang Chen ,  Mong-Song Liang

    IPC分类号： H01L21/8238 ,  H01L29/10 ,  H01L29/51 ,  H01L21/336 ,  H01L31/072

    CPC分类号： H01L29/517 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054

    摘要： At least one high-k device, and a method for forming the at least one high-k device, comprising the following. A structure having a strained substrate formed thereover. The strained substrate comprising at least an uppermost strained-Si epi layer. At least one dielectric gate oxide portion over the strained substrate. The at least one dielectric gate oxide portion having a dielectric constant of greater than about 4.0. A device over each of the at least one dielectric gate oxide portion to complete the least one high-k device. A method of forming the at least one high-k device.

    摘要翻译： 至少一个高k装置和用于形成至少一个高k装置的方法包括以下。 具有在其上形成的应变衬底的结构。 应变衬底包括至少最上层的应变Si外延层。 在应变衬底上的至少一个电介质栅极氧化物部分。 所述至少一个电介质栅极氧化物部分具有大于约4.0的介电常数。 在所述至少一个电介质栅极氧化物部分中的每一个上方的器件，以完成所述至少一个高k器件。 一种形成所述至少一个高k装置的方法。

    Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices
    10.
    发明授权
    Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices 有权
    双栅电介质方案：用于高性能器件的SiON和低功率器件的高k

    公开(公告)号：US06890811B2

    公开(公告)日：2005-05-10

    申请号：US10679768

    申请日：2003-10-06

    申请人： Tou-Hung Hou ,  Ming-Fang Wang ,  Chi-Chun Chen ,  Chih-Wei Yang ,  Liang-Gi Yao ,  Shih-Chang Chen

    发明人： Tou-Hung Hou ,  Ming-Fang Wang ,  Chi-Chun Chen ,  Chih-Wei Yang ,  Liang-Gi Yao ,  Shih-Chang Chen

    IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L29/76

    CPC分类号： H01L21/823456 ,  H01L21/823462

    摘要： A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT

    摘要翻译： 描述了可扩展以满足对于50nm和70nm技术节点的要求的形成双栅极电介质层的方法。 衬底具有分离器件区域的STI区域。 界面层和高k电介质层依次沉积在衬底上。 在一个器件区域上去除两个层，并且在暴露的器件区域上生长具有EOT <10nm的超薄氮氧化硅层。 在SiON介电层的生长期间，高k电介质层退火。 高k电介质层由金属氧化物或其硅酸盐或铝酸盐形成，并且能够以具有抑制的漏电流的EOT <1.8nm制造低功率器件。 当形成多个栅极时，该方法与双重或三重氧化物厚度工艺兼容。