公开(公告)号：US20160281225A1

公开(公告)日：2016-09-29

申请号：US14959333

申请日：2015-12-04

申请人： Minjong KIM ,  Jung-soo YOON ,  Jang-Hee LEE ,  Jongwon HONG

发明人： Minjong KIM ,  Jung-soo YOON ,  Jang-Hee LEE ,  Jongwon HONG

IPC分类号： C23C16/455 ,  C23C16/50

CPC分类号： C23C16/455 ,  C23C16/505 ,  H01J37/3244 ,  H01J37/32623 ,  H01J37/32633

摘要： A deposition apparatus includes a chuck in a process chamber, the chuck having a top surface on which a substrate is loaded, a showerhead disposed over the chuck, and a fence extension disposed in the process chamber. Plasma is generated in a space between the showerhead and the loaded substrate during a deposition process. The fence extension at least partially confines the plasma in the space during the deposition process, thereby enabling improved thickness uniformity and reliability of a layer deposited on the loaded substrate during the deposition process.

摘要翻译： 沉积设备包括处理室中的卡盘，卡盘具有其上装载有基底的顶表面，设置在卡盘上方的喷头和设置在处理室中的护栏延伸部。 在沉积过程中，等离子体在喷淋头和装载的基板之间的空间中产生。 栅栏延伸部在沉积工艺期间至少部分地将等离子体限制在空间中，从而能够在沉积工艺期间改善沉积在装载的衬底上的层的厚度均匀性和可靠性。

公开(公告)号：US20160064193A1

公开(公告)日：2016-03-03

申请号：US14734183

申请日：2015-06-09

申请人： Hogon KIM ,  Hyunsu KIM ,  Jang-Hee LEE ,  Gilheyun CHOI ,  Jongwon HONG

发明人： Hogon KIM ,  Hyunsu KIM ,  Jang-Hee LEE ,  Gilheyun CHOI ,  Jongwon HONG

IPC分类号： H01J37/32

CPC分类号： H01J37/32165 ,  H01J37/32091 ,  H01J37/32174

摘要： A semiconductor manufacturing apparatus includes a lower electrode, an upper electrode, first and second high-frequency power sources, and a controller. The lower electrode is disposed in a process chamber, and the upper electrode is disposed over the lower electrode in the process chamber. The first high-frequency power source is connected to one of the lower electrode and the upper electrode, and the second high-frequency power source is connected to one of the lower electrode and the upper electrode. The controller is connected to the first and second high-frequency power sources. The first high-frequency power source generates a first high-frequency power used to perform a first capacitively coupled plasma (CCP) process. The second high-frequency power source generates a second high-frequency power used to perform a second CCP process. The controller controls the second high-frequency power source to interrupt the second high-frequency power during the first CCP process.

摘要翻译： 半导体制造装置包括下电极，上电极，第一高频电源和第二高频电源以及控制器。 下电极设置在处理室中，上电极设置在处理室中的下电极之上。 第一高频电源连接到下电极和上电极中的一个，第二高频电源连接到下电极和上电极之一。 控制器连接到第一和第二高频电源。 第一高频电源产生用于执行第一电容耦合等离子体（CCP）过程的第一高频功率。 第二高频电源产生用于执行第二CCP处理的第二高频电源。 控制器控制第二高频电源，以在第一CCP过程中中断第二高频电源。

公开(公告)号：US20090256177A1

公开(公告)日：2009-10-15

申请号：US12453198

申请日：2009-05-01

申请人： Hee-Sook PARK ,  Gil-Heyun CHOI ,  Chang-Won LEE ,  Byung-Hak LEE ,  Sun-Pil YOUN ,  Dong-Chan LIM ,  Jae-Hwa PARK ,  Jang-Hee LEE ,  Woong-Hee SOHN

发明人： Hee-Sook PARK ,  Gil-Heyun CHOI ,  Chang-Won LEE ,  Byung-Hak LEE ,  Sun-Pil YOUN ,  Dong-Chan LIM ,  Jae-Hwa PARK ,  Jang-Hee LEE ,  Woong-Hee SOHN

IPC分类号： H01L29/80 ,  H01L23/498 ,  H01L23/52

CPC分类号： H01L29/4933 ,  C23C16/42 ,  H01L21/28061 ,  H01L21/28194 ,  H01L21/28556 ,  H01L21/76846 ,  H01L29/517

摘要： In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.

摘要翻译： 在欧姆层和形成欧姆层的方法中，包括欧姆层的栅极结构和具有欧姆层的金属布线，欧姆层使用包含钨和硅的钨硅化物形成，原子比在约 1:5至约1:15。 可以在室内使用包含钨源气体和硅源气体的反应气体，在约1.0:25.0至约1.0:16.0.0的范围内的分压比获得硅化钨。 反应气体可以具有在室的总内部压力的约2.05％至约30.0％的范围内的分压。 当欧姆层用于诸如栅极结构或金属布线的导电结构时，导电结构可以具有降低的电阻。

公开(公告)号：US20080073692A1

公开(公告)日：2008-03-27

申请号：US11773362

申请日：2007-07-03

申请人： Jang-Hee LEE ,  Geum-Jung SEONG ,  Byung-Hee KIM ,  Tae-Ho CHA ,  Hee-Sook PARK

发明人： Jang-Hee LEE ,  Geum-Jung SEONG ,  Byung-Hee KIM ,  Tae-Ho CHA ,  Hee-Sook PARK

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/28061 ,  H01L29/66825

摘要： A method of forming a semiconductor device includes sequentially first and second tungsten silicide layers on a silicon layer. The first tungsten silicide layer is in a substantially amorphous state and a ratio of tungsten to silicon in the first tungsten silicide layer is about 1:4.5˜about 1:9.

摘要翻译： 形成半导体器件的方法在硅层上依次包括第一和第二硅化钨层。 第一硅化钨层处于基本非晶态，并且第一硅化钨层中钨与硅的比例为约1:4.5〜约1:9。

公开(公告)号：US20060223252A1

公开(公告)日：2006-10-05

申请号：US11379350

申请日：2006-04-19

申请人： Jae-Hwa PARK ,  Jang-Hee LEE ,  Dae-Yong KIM ,  Hee-Sook PARK

发明人： Jae-Hwa PARK ,  Jang-Hee LEE ,  Dae-Yong KIM ,  Hee-Sook PARK

IPC分类号： H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/823828 ,  H01L21/823835

摘要： In one embodiment, a semiconductor device comprises a semiconductor substrate and a doped conductive layer formed over the semiconductor substrate. A diffusion barrier layer is formed over the doped conductive layer. The diffusion barrier layer comprises an amorphous semiconductor material. After forming the diffusion barrier layer, a heat treatment process may be additionally performed thereon. An ohmic contact layer is formed over the diffusion barrier layer. A metal barrier layer is formed over the ohmic contact layer. A metal layer is formed over the metal barrier layer.

摘要翻译： 在一个实施例中，半导体器件包括形成在半导体衬底上的半导体衬底和掺杂导电层。 在掺杂导电层上方形成扩散阻挡层。 扩散阻挡层包括非晶半导体材料。 在形成扩散阻挡层之后，还可以在其上进行热处理工艺。 在扩散阻挡层上形成欧姆接触层。 金属阻挡层形成在欧姆接触层上。 在金属阻挡层上形成金属层。