-
公开(公告)号：US20060095727A1
公开(公告)日：2006-05-04
申请号：US11304818
申请日：2005-12-16
申请人： Minoru Okamoto , Katsuhiko Ueda
发明人： Minoru Okamoto , Katsuhiko Ueda
IPC分类号： G06F9/40
CPC分类号： G06F9/30196 , G06F9/30181
摘要： An information processing device for sequentially reading and executing programs stored in memory means, including: a program counter for outputting an address for reading a program to the memory means; an instruction decoder for decoding instructions read from the memory means in response to a control signal indicating a period in which the types of codes used in at least a field among fields constituting an instruction in the program are limited to a predetermined number or less; and controlled means for performing processing corresponding to the decoded results output from the instruction decoder. The instruction decoder has a reconfigurable circuit for changing the circuit configuration in response to the control signal so that the decoding is performed based on a relationship between codes in a field in which the types of codes used are limited and decoded results, the relationship being set so that the number of times of change of bit values in the field is reduced.
摘要翻译： 一种用于顺序读取和执行存储在存储装置中的程序的信息处理装置，包括：程序计数器，用于将用于读取程序的地址输出到存储装置; 指令解码器，用于响应于指示在构成程序中的指令的至少一个字段中使用的代码的类型被限制为预定数量或更少的周期的控制信号来解码从存储器装置读取的指令; 以及用于执行与从指令解码器输出的解码结果对应的处理的控制装置。 指令解码器具有可重构电路，用于响应于控制信号改变电路配置，使得基于所使用的代码的类型的码中的码之间的关系进行解码，并且解码结果，该关系被设置 使得字段中比特值的改变次数减少。
-
公开(公告)号：US07774281B2
公开(公告)日：2010-08-10
申请号：US11152085
申请日：2005-06-15
申请人： Minoru Okamoto , Katsuhiko Ueda , Shirou Yoshioka , Tetsuji Kishi
发明人： Minoru Okamoto , Katsuhiko Ueda , Shirou Yoshioka , Tetsuji Kishi
IPC分类号： G06F21/00
CPC分类号： G06F21/10
摘要： A terminal device transmits device information thereof and a request for acquiring information contents to a contents distribution device. The contents distribution device generates a request for distributing a program for materializing the information contents in the terminal device based on the information contents designated in the acquisition request and the device information, and transmits a license request for using a function standard required for realizing the function to a license management device. The license management device receives the usage license request and correspondingly transmits an authorization for using the function standard to the program distribution device and the contents distribution device. The program distribution device transmits the program to the terminal device only when the usage authorization is received. The contents distribution device transmits the information contents to the terminal device only when the usage authorization is received.
摘要翻译： 终端装置向内容发布装置发送其设备信息和获取信息内容的请求。 内容分发装置根据获取请求中指定的信息内容和设备信息生成分发用于实现终端装置中的信息内容的程序的请求，并发送使用实现功能所需的功能标准的许可请求 到许可证管理设备。 许可证管理装置接收使用许可证请求，并相应地向程序发布装置和内容分发装置发送使用功能标准的授权。 程序分发装置仅在接收到使用授权时将程序发送到终端装置。 内容分发装置仅在接收到使用授权时才将该信息内容发送到终端装置。
-
公开(公告)号：US07058792B2
公开(公告)日：2006-06-06
申请号：US10485547
申请日：2002-08-01
申请人： Minoru Okamoto , Katsuhiko Ueda
发明人： Minoru Okamoto , Katsuhiko Ueda
IPC分类号： G06F9/30
CPC分类号： G06F9/30196 , G06F9/30181
摘要： An information processing device for sequentially reading and executing programs stored in memory means, including: a program counter for outputting an address for reading a program to the memory means; an instruction decoder for decoding instructions read from the memory means in response to a control signal indicating a period in which the types of codes used in at least a field among fields constituting an instruction in the program are limited to a predetermined number or less; and controlled means for performing processing corresponding to the decoded results output from the instruction decoder. The instruction decoder has a reconfigurable circuit for changing the circuit configuration in response to the control signal so that the decoding is performed based on a relationship between codes in a field in which the types of codes used are limited and decoded results, the relationship being set so that the number of times of change of bit values in the field is reduced.
摘要翻译： 一种用于顺序读取和执行存储在存储装置中的程序的信息处理装置，包括：程序计数器，用于将用于读取程序的地址输出到存储装置; 指令解码器，用于响应于指示在构成程序中的指令的至少一个字段中使用的代码的类型被限制为预定数量或更少的周期的控制信号来解码从存储器装置读取的指令; 以及用于执行与从指令解码器输出的解码结果对应的处理的控制装置。 指令解码器具有可重构电路，用于响应于控制信号改变电路配置，使得基于所使用的代码的类型的码中的码之间的关系进行解码，并且解码结果，该关系被设置 使得字段中比特值的改变次数减少。
-
公开(公告)号：US20060021025A1
公开(公告)日：2006-01-26
申请号：US11152085
申请日：2005-06-15
申请人： Minoru Okamoto , Katsuhiko Ueda , Shirou Yoshioka , Tetsuji Kishi
发明人： Minoru Okamoto , Katsuhiko Ueda , Shirou Yoshioka , Tetsuji Kishi
IPC分类号： G06F12/14
CPC分类号： G06F21/10
摘要： A terminal device transmits device information thereof and a request for acquiring information contents to a contents distribution device. The contents distribution device generates a request for distributing a program for materializing the information contents in the terminal device based on the information contents designated in the acquisition request and the device information, and transmits a license request for using a function standard required for realizing the function to a license management device. The license management device receives the usage license request and correspondingly transmits an authorization for using the function standard to the program distribution device and the contents distribution device. The program distribution device transmits the program to the terminal device only when the usage authorization is received. The contents distribution device transmits the information contents to the terminal device only when the usage authorization is received.
摘要翻译： 终端装置向内容发布装置发送其设备信息和获取信息内容的请求。 内容分发装置根据获取请求中指定的信息内容和设备信息生成分发用于实现终端装置中的信息内容的程序的请求，并发送使用实现功能所需的功能标准的许可请求 到许可证管理设备。 许可证管理装置接收使用许可证请求，并相应地向程序发布装置和内容分发装置发送使用功能标准的授权。 程序分发装置仅在接收到使用授权时将程序发送到终端装置。 内容分发装置仅在接收到使用授权时才将该信息内容发送到终端装置。
-
公开(公告)号：US20050283483A1
公开(公告)日：2005-12-22
申请号：US11152091
申请日：2005-06-15
申请人： Minoru Okamoto , Katsuhiko Ueda , Shirou Yoshioka , Tetsuji Kishi
发明人： Minoru Okamoto , Katsuhiko Ueda , Shirou Yoshioka , Tetsuji Kishi
IPC分类号： G06F9/445 , G06F13/00 , G06F15/00 , G06F17/30 , G06Q30/06 , G06Q50/00 , H04L29/08 , H04N7/173
CPC分类号： H04L67/303 , H04L67/04 , H04L67/18 , H04N7/17318
摘要： A terminal device transmits device information thereof and a request for acquiring information contents to a contents distribution device. The contents distribution device generates a request for distributing a program for materializing the information contents in the terminal device based on the information contents designated in the acquisition request and the device information, and transmits the distribution request to a program distribution device and transmits the device information to an inspection device. The program distribution device transmits the program in the distribution request to the inspection device. The inspection device inspects a materialization state of the information contents in the terminal device based on the program and the device information and transmits a result of the inspection to the program distribution device and the contents distribution device. The program distribution device transmits the program to the terminal device and the contents distribution device transmits the information contents to the terminal device only when the inspection result is favorable.
摘要翻译： 终端装置向内容发布装置发送其设备信息和获取信息内容的请求。 内容分发装置根据获取请求中指定的信息内容和设备信息生成分发用于实现终端装置中的信息内容的程序的请求，并将分发请求发送给节目发布装置，并发送装置信息 到检查装置。 程序分配装置将分发请求中的程序发送到检查装置。 检查装置基于程序和设备信息检查终端装置中的信息内容的实现状态，并将检查结果发送给程序发布装置和内容分发装置。 程序发布装置将程序发送到终端装置，并且内容分发装置仅在检查结果有利时才向终端装置发送信息内容。
-
6.发明授权Interleaved memory wherein plural memory means comprising plural banks output data simultaneously while a control unit sequences the addresses in ascending and descending directions 失效交错存储器，其中包括多个存储体的多个存储器装置同时输出数据，同时控制单元以上升和下降方向排列地址
公开(公告)号：US5537577A
公开(公告)日：1996-07-16
申请号：US58530
申请日：1993-05-06
CPC分类号： G06F12/0607 , F02B2075/025
摘要： An interleaving memory system having a first memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, a second memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, and a holding device for holding data from one of the banks of one of the first memory device and the second memory device to delay an output of the data for 1/2 cycle time for sequential addressing. A controller controls first and second selection devices wherein the 0-bank and the 1-bank are alternatively selected when data is outputted either in an ascending order of consecutive addresses from the even-numbered addresses in the first or second memory devices, or in a descending order of consecutive addresses from the odd-numbered addresses in the first or second memory devices. Also, the first holding device and a bank whose output is not held by the first holding device are alternatively selected when data is outputted either in a descending order of consecutive addresses from the even-numbered addresses in the first memory device, or in an ascending order of consecutive addresses from the odd-numbered addresses in the first memory device. The second holding device and a bank whose output is not held by the second holding device are similarly alternatively selected.
摘要翻译： 一种交织存储器系统，具有第一存储器装置，该第一存储器装置包括一个0组和一个一组，用于同时从该第一存储区输出来自0组的偶数地址的数据和奇数地址的数据;第二存储器装置 包括0行和1行，用于从0行同时从偶数行地址输出数据和来自1行的奇数地址的数据;以及保持装置，用于从一个存储体中的一个存储区中保存数据 第一存储器件和第二存储器件之一，用于将数据的输出延迟1/2个周期时间用于顺序寻址。 控制器控制第一和第二选择装置，其中当从第一或第二存储装置中的偶数地址以连续地址的升序输出数据时，交替地选择0组和1组，或者在 来自第一或第二存储器件中的奇数地址的连续地址的降序。 此外，当从第一存储装置中的偶数地址以连续地址的降序输出数据时，交替地选择第一保持装置和输出未被第一保持装置保持的存储体，或者以升序 来自第一存储设备中的奇数地址的连续地址的顺序。 类似地，第二保持装置和输出没有被第二保持装置保持的组。
-
7.发明授权Inserting decoder reconfiguration instruction for routine with limited number of instruction types recoded for reduced bit changes 有权为有限数量的指令类型插入用于程序的解码器重新配置指令，重新编码以减少位变化公开(公告)号：US07287149B2
公开(公告)日：2007-10-23
申请号：US11304818
申请日：2005-12-16
申请人： Minoru Okamoto , Katsuhiko Ueda
发明人： Minoru Okamoto , Katsuhiko Ueda
CPC分类号： G06F9/30196 , G06F9/30181
摘要： An information processing method for coding a program to enable an information processing device having an instruction decoder having a reconfigurable circuit, comprises the steps of: simulating execution of the program to obtain a history of instructions executed; extracting a routine in which a number of types of codes used in at least a field among fields constituting an instruction is limited to a predetermined number or less, from the program based on the history; inserting an instruction for changing circuit configuration of the reconfigurable circuit at start and end of the routine; allocating codes so that number of times of change of bit values in a field in which the number of types of codes used are limited is reduced for the routine; and converting a program obtained in the step of inserting an instruction to codes according to the allocation for the routine.
摘要翻译： 一种用于编码程序以使具有具有可重构电路的指令解码器的信息处理装置的信息处理方法包括以下步骤：模拟程序的执行以获得执行的指令的历史; 提取一种程序，其中从构成指令的字段中的至少一个字段中使用的代码数量的数量被限制为预定数量或更少的例程; 在程序的开始和结束时插入用于改变可重新配置电路的电路配置的指令; 分配代码，使得在所使用的代码类型的数量的数量被限制的字段中的比特值的改变次数减少; 以及根据所述例程的分配将在指令插入指令的步骤中获得的程序转换成代码。
-
公开(公告)号：US20050163233A1
公开(公告)日：2005-07-28
申请号：US11022811
申请日：2004-12-28
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2n bits in length.
摘要翻译： 数字信号处理器包括被配置为执行指令的功能单元。 功能单元与第三数据和第四数据的第二最小数据的确定并行地确定第一数据和第二数据的第一最小数据。 功能单元输出包括第一最小数据和第二最小数据的处理数据。 第一最小数据和第二最小数据的每个位长度等于n位长度。 处理数据的位长度等于2n位长。
-
公开(公告)号：US06751773B2
公开(公告)日：2004-06-15
申请号：US09833061
申请日：2001-04-12
IPC分类号： H03M1303
CPC分类号： H03M13/23
摘要： A coding apparatus includes shift register, input register and logical operation section. The shift register performs bit shifting on an input bit sequence and stores one bit of the input bit sequence after another. The input register stores coefficients of terms on respective orders of a generator polynomial. The logical operation section obtains logical products of the respective bits stored on the shift register and associated bits stored on the input register and a logical product of each one bit input to the shift register and an associated bit stored on the input register so that the earlier a bit of the input bit sequence was input, the higher-order one of the coefficients in the terms of the polynomial the input bit is associated with. Next, the logical operation section derives an exclusive logical sum of the products and then outputs the sum as a bit of a code sequence.
摘要翻译： 编码装置包括移位寄存器，输入寄存器和逻辑运算部。 移位寄存器在输入位序列上执行位移位，并将输入位序列的一位相继存储。 输入寄存器存储关于生成多项式的各个阶的项的系数。 逻辑运算部分获得存储在移位寄存器上的相应位的逻辑积和存储在输入寄存器上的相关位以及输入到移位寄存器的每一位的逻辑积和存储在输入寄存器上的关联位， 输入一位输入比特序列，输入比特关联的多项式项中的系数中的高阶一个。 接下来，逻辑运算部分导出乘积的异或逻辑和，然后输出和作为代码序列的位。
-
公开(公告)号：US06477661B2
公开(公告)日：2002-11-05
申请号：US09974807
申请日：2001-10-12
IPC分类号： G06F1100
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： A method of operating a digital signal processor is provided. The digital signal processor may be provided as a radio communication mobile station, a radio communication base station apparatus, or a CDMA radio communication system. Each path metric PM1 and PM0 of an old state is added to each branch metric BM1 and BM0 separately. A path metric of a new state N is formed by comparing the value of PM1+BM1 to the value of PM0+BM0. A path metric of a new state N+2k−2 is formed by comparing the value of PM1+BM0 to PM0+BM1.
摘要翻译： 提供了一种操作数字信号处理器的方法。 数字信号处理器可以被提供为无线电通信移动台，无线电通信基站装置或CDMA无线电通信系统。 将旧状态的每个路径度量PM1和PM0分别添加到每个分支量度BM1和BM0。 通过将PM1 + BM1的值与PM0 + BM0的值进行比较来形成新状态N的路径度量。 通过将PM1 + BM0的值与PM0 + BM1进行比较来形成新状态N + 2k-2的路径度量。
-
-
-
-
-
-
-
-
-
搜索结果
44 条记录 (耗时 0.019 秒)
