摘要:
A fluid transferring apparatus achieves a two-dimensional flow of fluid with high efficiency and at low noise by imitating a Weis-Fogh mechanism with use of a simple mechanism. In the fluid transferring apparatus, a wing assembly X comprised of a predetermined number of plate-like wings is provided in a transverse direction of a flow passage. A wing assembly X is supported by a link of a crank mechanism which is constituted of a crank rotated by a motor, a slider slidable in a direction orthogonal to a direction of a flow in a flow passage and the link coupling the crank with the slider, so that rotational motion of the crank is transmitted to the slider as a reciprocal movement. While an angle of attack of each wing is changed by oscillating action of the link, each wing is moved in a transverse direction of the flow passage as the link is reciprocated, thereby achieving transfer of fluid.
摘要:
A crossflow fan includes a rotary impeller formed by curved blades 42. Each of the blades 42 has an outer peripheral edge 43 close to the centrifugal side of the impeller and an inner peripheral edge 44 close to the rotation axis side of the impeller. A plurality of cutouts 45 are formed in the outer peripheral edge 43 and spaced apart at predetermined intervals. Dimples 48 for changing a boundary layer from a laminar flow to a turbulent flow are formed in a negative pressure surface 4q of each blade 42 in the vicinity of the outer peripheral edge 43 to prevent the gas flowing around the blade 42 from separating from the blade 42.
摘要:
There are provided a ferrite carrier core material for an electrophotographic developer, which contain 10 to 30% by weight of Mn, 1.0 to 3.0% by weight of Mg, 0.3 to 1.5% by weight of Ti and 40 to 60% by weight of Fe, a ferrite carrier for an electrophotographic developer obtained by coating the ferrite core material, and an electrophotographic developer using the ferrite carrier.
摘要:
A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.
摘要:
A phase adjustment circuit for discretely adjusting a phase of a data signal and that of a clock signal, the phase adjustment circuit including: a delay line for delaying the clock signal to produce a delayed clock signal; a phase comparator for comparing the phase of the data signal with that of the delayed clock signal; a delay control section for outputting a delay control signal based on the comparison result from the phase comparator; and a delay control section for outputting a delay control signal based on a frequency of the clock signal. The delay line determines a delay amount of the delayed clock signal with respect to the clock signal based on the control signals.
摘要:
It is an object of the present invention to solve the problem of a drop in precision in conventional systems using a square pyramid type five-hole probe due to the drop in atmospheric pressure in high altitude ranges, and to provide a wide velocity range flight velocity vector measurement system that can prevent a drop in measurement precision. Furthermore, it is also an object of the present invention to provide a method for eliminating the effects of detection fluctuations caused by adhering water droplets, ice particles or dust in a wide velocity range flight velocity vector measurement system. The flight velocity vector measurement probe of the present invention comprises means in which a static pressure hole is formed in the tube wall surface of the probe, so that a static pressure value is obtained from the pressure detected by this static pressure hole, the Mach number M is calculated on the basis of an equation approximated by a fourth-order polynomial of the static pressure/total pressure signal and the angle of attack, and in cases where an abnormal detection value is detected, this is replaced by the preceding detection value.
摘要:
An air discharge outlet comprises line air discharge outlets (35) and corner air discharge outlets (36). The line air discharge outlets (35) are so formed as to extend, respectively, along four sides of a casing bottom part having four side parts and four corner parts wherein the side and corner parts are formed in contiguous relationship to one another. The corner air discharge outlets (36) are formed, respectively, in the four casing corner parts so that each corner air discharge outlet (36) establishes connection between adjacent ones of the line air discharge outlets (35). And, each line air discharge outlet (35) is provided with a swing vane (38) swingable about a longitudinal shaft (41) of each line air discharge outlet (35). Each corner air discharge outlet (36) is provided with a fixed stationary vane (39).
摘要:
A phase adjustment circuit for discretely adjusting a phase of a data signal and that of a clock signal, the phase adjustment circuit including: a delay line for delaying the clock signal to produce a delayed clock signal; a phase comparator for comparing the phase of the data signal with that of the delayed clock signal; a delay control section for outputting a delay control signal based on the comparison result from the phase comparator; and a delay control section for outputting a delay control signal based on a frequency of the clock signal. The delay line determines a delay amount of the delayed clock signal with respect to the clock signal based on the control signals.
摘要:
An analog equalizer includes a mixer and an analog delay circuit. The mixer mixes an input signal and a delayed signal output from the analog delay circuit to output a mixed signal. The analog delay circuit delays the mixed signal output from the mixer to output a delayed signal.
摘要:
The present invention provides a semiconductor integrated circuit system, having one master chip and a plurality of slave chips, for performing data transfer under a control of a predetermined clock. The system includes: a detection section for detecting a change in a state of the semiconductor integrated circuit system and for producing information indicating the detection result, the state including at least one of temperature and source voltage; and at least one clock phase adjustment section for receiving the information and for adjusting a phase of a clock used in transferring data output by the slave chip based on the information.