公开(公告)号：US07681154B2

公开(公告)日：2010-03-16

申请号：US11854591

申请日：2007-09-13

申请人： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Hiroya Shimizu ,  Satoshi Isa ,  Satoshi Itaya ,  Yukitoshi Hirose

发明人： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Hiroya Shimizu ,  Satoshi Isa ,  Satoshi Itaya ,  Yukitoshi Hirose

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5036

摘要： A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad. The main target variable is compared with a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.

摘要翻译： 公开了一种用于设计包括第一半导体芯片，第二半导体芯片和调整对象的装置的方法。 第一半导体芯片包括输入焊盘，第一电源焊盘和第一接地焊盘。 第二半导体芯片包括耦合到输入焊盘的输出焊盘。 调整对象被连接到第一和第二半导体芯片。 主要目标变量由输入电路芯片模型，频域中的第二半导体芯片的输出电路芯片模型和频域中的调整对象的目标阻抗模型计算。 考虑到输入焊盘和第一电源焊盘之间的第一电容器模型，在输入焊盘和第一接地焊盘之间的第二电容器模型，以及第一电容器模型 芯片内部电容器模型在第一个电源焊盘和第一个接地焊盘之间。 将主要目标变量与在频域中表示的预定约束进行比较，以决定调整目标的设计指南。

公开(公告)号：US20080072194A1

公开(公告)日：2008-03-20

申请号：US11854591

申请日：2007-09-13

申请人： Mitsuaki KATAGIRI ,  Satoshi Nakamura ,  Takashi Suga ,  Hiroya Shimizu ,  Satoshi Isa ,  Satoshi Itaya ,  Yukitoshi Hirose

发明人： Mitsuaki KATAGIRI ,  Satoshi Nakamura ,  Takashi Suga ,  Hiroya Shimizu ,  Satoshi Isa ,  Satoshi Itaya ,  Yukitoshi Hirose

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad. The main target variable is compared with a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.

摘要翻译： 公开了一种用于设计包括第一半导体芯片，第二半导体芯片和调整对象的装置的方法。 第一半导体芯片包括输入焊盘，第一电源焊盘和第一接地焊盘。 第二半导体芯片包括耦合到输入焊盘的输出焊盘。 调整对象被连接到第一和第二半导体芯片。 主要目标变量由输入电路芯片模型，频域中的第二半导体芯片的输出电路芯片模型和频域中的调整对象的目标阻抗模型计算。 考虑到输入焊盘和第一电源焊盘之间的第一电容器模型，在输入焊盘和第一接地焊盘之间的第二电容器模型，以及第一电容器模型 芯片内部电容器模型在第一个电源焊盘和第一个接地焊盘之间。 将主要目标变量与在频域中表示的预定约束进行比较，以决定调整目标的设计指南。

公开(公告)号：US07689944B2

公开(公告)日：2010-03-30

申请号：US11511438

申请日：2006-08-29

申请人： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Satoshi Isa ,  Yoji Nishio ,  Seiji Funaba ,  Yukitoshi Hirose

发明人： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Satoshi Isa ,  Yoji Nishio ,  Seiji Funaba ,  Yukitoshi Hirose

IPC分类号： G06F17/50

CPC分类号： H05K3/0005 ,  G06F17/5068 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K2201/10545 ,  H05K2201/10734 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.

摘要翻译： 公开了一种考虑半导体封装中所包括的半导体芯片的功率完整性来设计包括半导体封装的半导体器件的方法。 基于关于调整对象的目标信息来计算用于调整目标的目标变量，其中目标变量在频域中被表示，并且调整目标包括半导体封装的一部分。 将目标变量与在频域中表示的预定约束进行比较，以识别有问题的部分，其中有问题的部分对应于目标变量超过预定约束的频率区域。 决定设计指南来解决确定的问题部分。

公开(公告)号：US20070057380A1

公开(公告)日：2007-03-15

申请号：US11511438

申请日：2006-08-29

申请人： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Satoshi Isa ,  Yoji Nishio ,  Seiji Funaba ,  Yukitoshi Hirose

发明人： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Satoshi Isa ,  Yoji Nishio ,  Seiji Funaba ,  Yukitoshi Hirose

IPC分类号： H01L23/48

CPC分类号： H05K3/0005 ,  G06F17/5068 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K2201/10545 ,  H05K2201/10734 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.

摘要翻译： 公开了一种考虑半导体封装中所包括的半导体芯片的功率完整性来设计包括半导体封装的半导体器件的方法。 基于关于调整对象的目标信息来计算用于调整目标的目标变量，其中目标变量在频域中被表示，并且调整目标包括半导体封装的一部分。 将目标变量与在频域中表示的预定约束进行比较，以识别有问题的部分，其中有问题的部分对应于目标变量超过预定约束的频率区域。 决定设计指南来解决确定的问题部分。

公开(公告)号：US07694245B2

公开(公告)日：2010-04-06

申请号：US11710965

申请日：2007-02-27

申请人： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Yoji Nishio ,  Satoshi Isa ,  Satoshi Itaya

发明人： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Yoji Nishio ,  Satoshi Isa ,  Satoshi Itaya

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L23/50 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.

摘要翻译： 公开了一种用于设计半导体封装的方法，其中半导体封装包括半导体芯片和调整对象。 考虑到半导体芯片的输出电平从低电平变为高电平的第一转变状态来计算第一目标变量。 考虑到半导体芯片的输出电平从高电平变为低电平的第二过渡状态来计算第二目标变量。 选择第一和第二目标变量之一作为主要目标变量。 比较主要目标变量和在频域中表示的预定约束，以决定调整目标的设计指南。

公开(公告)号：US20070204251A1

公开(公告)日：2007-08-30

申请号：US11710965

申请日：2007-02-27

申请人： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Yoji Nishio ,  Satoshi Isa ,  Satoshi Itaya

发明人： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Yoji Nishio ,  Satoshi Isa ,  Satoshi Itaya

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L23/50 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.

摘要翻译： 公开了一种用于设计半导体封装的方法，其中半导体封装包括半导体芯片和调整对象。 考虑到半导体芯片的输出电平从低电平变为高电平的第一转变状态来计算第一目标变量。 考虑到半导体芯片的输出电平从高电平变为低电平的第二过渡状态来计算第二目标变量。 选择第一和第二目标变量之一作为主要目标变量。 比较主要目标变量和在频域中表示的预定约束，以决定调整目标的设计指南。

公开(公告)号：US20060227587A1

公开(公告)日：2006-10-12

申请号：US11384277

申请日：2006-03-21

申请人： Satoshi Nakamura ,  Takashi Suga ,  Mitsuaki Katagiri ,  Yukitoshi Hirose

发明人： Satoshi Nakamura ,  Takashi Suga ,  Mitsuaki Katagiri ,  Yukitoshi Hirose

IPC分类号： G11C5/06

CPC分类号： G11C5/04 ,  G11C5/063 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/0401 ,  G11C2029/3602 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/06568 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

摘要： Disclosed is a multichip package or system-in package which the logic chip includes a selector circuit which, by transmitting a test mode select signal or a test mode select command to the logic chip, enables access from a logic signal pin connected to the logic chip, to a memory control signal to each of the “m” number of memory chips; and the memory control signal, when viewed from the logic chip, is connected using a one-for-one wiring scheme or a one-for-up-to-m branch wiring scheme, between the selector circuit and each of the “m” number of memory chips. This multichip package or system-in package is low in noise and high in operational reliability.

摘要翻译： 公开了一种多芯片封装或系统级封装，其中逻辑芯片包括选择器电路，其通过将测试模式选择信号或测试模式选择命令发送到逻辑芯片，使得能够从连接到逻辑芯片的逻辑信号引脚 到存储器控制信号到每个“m”个存储器芯片; 并且当从逻辑芯片观察时，存储器控制信号使用一对一布线方案或一对多分支布线方案连接，在选择器电路和每个“m” 内存芯片数量 这种多芯片封装或系统级封装的噪声低，操作可靠性高。

公开(公告)号：US07851898B2

公开(公告)日：2010-12-14

申请号：US11384277

申请日：2006-03-21

申请人： Satoshi Nakamura ,  Takashi Suga ,  Mitsuaki Katagiri ,  Yukitoshi Hirose

发明人： Satoshi Nakamura ,  Takashi Suga ,  Mitsuaki Katagiri ,  Yukitoshi Hirose

IPC分类号： H01L23/538 ,  H01L23/52 ,  H01L25/18 ,  H01L25/065

CPC分类号： G11C5/04 ,  G11C5/063 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/0401 ,  G11C2029/3602 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/06568 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

摘要： Disclosed is a multichip package or system-in package which the logic chip includes a selector circuit which, by transmitting a test mode select signal or a test mode select command to the logic chip, enables access from a logic signal pin connected to the logic chip, to a memory control signal to each of the “m” number of memory chips; and the memory control signal, when viewed from the logic chip, is connected using a one-for-one wiring scheme or a one-for-up-to-m branch wiring scheme, between the selector circuit and each of the “m” number of memory chips. This multichip package or system-in package is low in noise and high in operational reliability.

摘要翻译： 公开了一种多芯片封装或系统级封装，其中逻辑芯片包括选择器电路，其通过将测试模式选择信号或测试模式选择命令发送到逻辑芯片，使得能够从连接到逻辑芯片的逻辑信号引脚 到存储器控制信号到每个“m”个存储器芯片; 并且当从逻辑芯片观察时，存储器控制信号使用一对一布线方案或一对多分支布线方案连接，在选择器电路和每个“m” 内存芯片数量 这种多芯片封装或系统级封装的噪声低，操作可靠性高。

公开(公告)号：US07315173B2

公开(公告)日：2008-01-01

申请号：US11236733

申请日：2005-09-28

申请人： Hiroki Funato ,  Takashi Suga ,  Kouichi Uesaka ,  Satoshi Nakamura

发明人： Hiroki Funato ,  Takashi Suga ,  Kouichi Uesaka ,  Satoshi Nakamura

IPC分类号： G01R27/04 ,  G01R31/302 ,  G01R29/12 ,  G01N27/60

CPC分类号： G01R29/0871 ,  G01R29/0814 ,  G01R29/0892 ,  G01R31/002

摘要： A method and apparatus for measuring an electric field distribution according to the present invention calculates a distribution of electric field intensity and its direction at arbitrary positions on the surface of the electronic apparatus or its circumference with use of data of measurement positions and measurement results of a potential distribution on a surface of an electronic apparatus. Further, it clearly indicates a flow of electromagnetic energy on the surface or in the circumference of the electronic apparatus by applying mathematical treatments to a magnetic field distribution at circumferential positions of the electronic apparatus. Thus, a distribution of high-frequency electric field generated from the electronic apparatus is measured with high accuracy.

摘要翻译： 根据本发明的用于测量电场分布的方法和装置使用测量位置和测量结果的数据来计算电子设备或其周围上的任意位置处的电场强度及其方向的分布 在电子设备的表面上的电位分布。 此外，通过对电子设备的圆周位置的磁场分布应用数学处理，清楚地表示电子设备的表面或周围的电磁能量的流动。 因此，以高精度测量从电子设备产生的高频电场的分布。

公开(公告)号：US20060071669A1

公开(公告)日：2006-04-06

申请号：US11236733

申请日：2005-09-28

申请人： Hiroki Funato ,  Takashi Suga ,  Kouichi Uesaka ,  Satoshi Nakamura

发明人： Hiroki Funato ,  Takashi Suga ,  Kouichi Uesaka ,  Satoshi Nakamura

IPC分类号： G01R27/04

CPC分类号： G01R29/0871 ,  G01R29/0814 ,  G01R29/0892 ,  G01R31/002

摘要： A method and apparatus for measuring an electric field distribution according to the present invention calculates a distribution of electric field intensity and its direction at arbitrary positions on the surface of the electronic apparatus or its circumference with use of data of measurement positions and measurement results of a potential distribution on a surface of an electronic apparatus. Further, it clearly indicates a flow of electromagnetic energy on the surface or in the circumference of the electronic apparatus by applying mathematical treatments to a magnetic field distribution at circumferential positions of the electronic apparatus. Thus, a distribution of high-frequency electric field generated from the electronic apparatus is measured with high accuracy.

摘要翻译： 根据本发明的用于测量电场分布的方法和装置使用测量位置和测量结果的数据来计算电子设备或其周围上的任意位置处的电场强度及其方向的分布 在电子设备的表面上的电位分布。 此外，通过对电子设备的圆周位置的磁场分布应用数学处理，清楚地表示电子设备的表面或周围的电磁能量的流动。 因此，以高精度测量从电子设备产生的高频电场的分布。