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    Method for designing device, system for aiding to design device, and computer program product therefor
    1.
    发明授权
    Method for designing device, system for aiding to design device, and computer program product therefor 失效
    设计装置的方法，辅助设计装置的系统及其计算机程序产品

    公开(公告)号：US07681154B2

    公开(公告)日：2010-03-16

    申请号：US11854591

    申请日：2007-09-13

    申请人： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Hiroya Shimizu ,  Satoshi Isa ,  Satoshi Itaya ,  Yukitoshi Hirose

    发明人： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Hiroya Shimizu ,  Satoshi Isa ,  Satoshi Itaya ,  Yukitoshi Hirose

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/5036

    摘要： A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad. The main target variable is compared with a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.

    摘要翻译： 公开了一种用于设计包括第一半导体芯片，第二半导体芯片和调整对象的装置的方法。 第一半导体芯片包括输入焊盘，第一电源焊盘和第一接地焊盘。 第二半导体芯片包括耦合到输入焊盘的输出焊盘。 调整对象被连接到第一和第二半导体芯片。 主要目标变量由输入电路芯片模型，频域中的第二半导体芯片的输出电路芯片模型和频域中的调整对象的目标阻抗模型计算。 考虑到输入焊盘和第一电源焊盘之间的第一电容器模型，在输入焊盘和第一接地焊盘之间的第二电容器模型，以及第一电容器模型 芯片内部电容器模型在第一个电源焊盘和第一个接地焊盘之间。 将主要目标变量与在频域中表示的预定约束进行比较，以决定调整目标的设计指南。

    METHOD FOR DESIGNING DEVICE, SYSTEM FOR AIDING TO DESIGN DEVICE, AND COMPUTER PROGRAM PRODUCT THEREFOR
    2.
    发明申请
    METHOD FOR DESIGNING DEVICE, SYSTEM FOR AIDING TO DESIGN DEVICE, AND COMPUTER PROGRAM PRODUCT THEREFOR 失效
    用于设计设备的方法，用于设计设备的系统，以及计算机程序产品

    公开(公告)号：US20080072194A1

    公开(公告)日：2008-03-20

    申请号：US11854591

    申请日：2007-09-13

    申请人： Mitsuaki KATAGIRI ,  Satoshi Nakamura ,  Takashi Suga ,  Hiroya Shimizu ,  Satoshi Isa ,  Satoshi Itaya ,  Yukitoshi Hirose

    发明人： Mitsuaki KATAGIRI ,  Satoshi Nakamura ,  Takashi Suga ,  Hiroya Shimizu ,  Satoshi Isa ,  Satoshi Itaya ,  Yukitoshi Hirose

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad. The main target variable is compared with a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.

    摘要翻译： 公开了一种用于设计包括第一半导体芯片，第二半导体芯片和调整对象的装置的方法。 第一半导体芯片包括输入焊盘，第一电源焊盘和第一接地焊盘。 第二半导体芯片包括耦合到输入焊盘的输出焊盘。 调整对象被连接到第一和第二半导体芯片。 主要目标变量由输入电路芯片模型，频域中的第二半导体芯片的输出电路芯片模型和频域中的调整对象的目标阻抗模型计算。 考虑到输入焊盘和第一电源焊盘之间的第一电容器模型，在输入焊盘和第一接地焊盘之间的第二电容器模型，以及第一电容器模型 芯片内部电容器模型在第一个电源焊盘和第一个接地焊盘之间。 将主要目标变量与在频域中表示的预定约束进行比较，以决定调整目标的设计指南。

    Semiconductor device or printed wiring board design method and design support system that implements settings by using a semiconductor device model that expresses parasitic elements that occur when packaged
    7.
    发明申请
    Semiconductor device or printed wiring board design method and design support system that implements settings by using a semiconductor device model that expresses parasitic elements that occur when packaged 审中-公开
    半导体器件或印刷线路板设计方法和设计支持系统，通过使用表示在封装时发生的寄生元件的半导体器件模型来实现设置

    公开(公告)号：US20090327981A1

    公开(公告)日：2009-12-31

    申请号：US12457930

    申请日：2009-06-25

    申请人： Satoshi Nakamura ,  Tsutomu Hara ,  Mitsuaki Katagiri ,  Yukitoshi Hirose ,  Satoshi Itaya ,  Ken Iwakura

    发明人： Satoshi Nakamura ,  Tsutomu Hara ,  Mitsuaki Katagiri ,  Yukitoshi Hirose ,  Satoshi Itaya ,  Ken Iwakura

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F2217/78 ,  H05K1/181 ,  H05K3/0005

    摘要： Correction circuit models are acquired for correcting electrical characteristic parameters that change upon mounting on a board. The correction circuit models are added to a separate model that represents a separate semiconductor device in isolation to create a semiconductor device model that represents the semiconductor device in a board-mounted state. An equivalent circuit model that represents an adjustment-object system is connected to the semiconductor device model that was created, and based on the semiconductor device model to which the equivalent circuit model is connected, adjustment-object values relating to the adjustment-object system are calculated. These adjustment-object values are compared with limit values that were determined in advance, and based on the results of comparison, a design guide is determined for adjusting the adjustment-object system.

    摘要翻译： 获取校正电路模型，用于校正在电路板上安装时变化的电特性参数。 校正电路模型被添加到单独的模型中，该模型表示隔离的单独的半导体器件以产生表示板安装状态的半导体器件的半导体器件模型。 表示调整对象系统的等效电路模型连接到所创建的半导体器件模型，并且基于与等效电路模型相连接的半导体器件模型，与调整对象系统相关的调整对象值为 计算。 将这些调整对象值与预先确定的限制值进行比较，并且基于比较结果，确定调整对象系统的设计指南。

    Test method and interposer used therefor
    10.
    发明授权
    Test method and interposer used therefor 失效
    用于此的测试方法和插入器

    公开(公告)号：US08680881B2

    公开(公告)日：2014-03-25

    申请号：US13044717

    申请日：2011-03-10

    申请人： Yutaka Uematsu ,  Hideki Osaka ,  Satoshi Nakamura ,  Satoshi Muraoka ,  Mitsuaki Katagiri ,  Ken Iwakura ,  Yukitoshi Hirose

    发明人： Yutaka Uematsu ,  Hideki Osaka ,  Satoshi Nakamura ,  Satoshi Muraoka ,  Mitsuaki Katagiri ,  Ken Iwakura ,  Yukitoshi Hirose

    IPC分类号： G01R31/00

    CPC分类号： G01R31/2889

    摘要： An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.

    摘要翻译： 安装有作为测试对象的集成电路的插入器设置有用于检测与集成电路的各个端子相对应的电流的开关和探头。 然后，通过作为与集成电路的电源端子连接并断开的开关的测试基板将测试图形信号输入到集成电路。 如果集成电路正常工作，并且集成电路的所有端子的电流值都在容差内，则连接到关断开关的电源端子被识别为可以被去除的端子。