公开(公告)号：US6097622A

公开(公告)日：2000-08-01

申请号：US867792

申请日：1997-06-03

申请人： Mitsuru Shimizu ,  Hiroyuki Takenaka ,  Sumio Tanaka

发明人： Mitsuru Shimizu ,  Hiroyuki Takenaka ,  Sumio Tanaka

IPC分类号： G11C11/22 ,  G11C11/404 ,  G11C14/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C11/22

摘要： A ferroelectric memory having a memory cell array or a plurality of memory cell arrays, word lines, where each memory cell array includes word lines. The memory also includes a plurality of plate lines, where each memory cell array includes some of the plate lines and the word line corresponds with some of the plate lines, a bit line, a word line select circuit for selecting among the word lines, and plurality of plate line select circuits, where each of the plate line select circuit is coupled to an associated plate line.

摘要翻译： 具有存储单元阵列或多个存储单元阵列的铁电存储器，字线，其中每个存储单元阵列包括字线。 存储器还包括多个板线，其中每个存储单元阵列包括一些板线，并且字线对应于一些板线，位线，用于在字线之间选择的字线选择电路和 多个板线选择电路，其中每个板线选择电路耦合到相关的板线。

公开(公告)号：US6046926A

公开(公告)日：2000-04-04

申请号：US170104

申请日：1998-10-13

申请人： Sumio Tanaka ,  Hiroyuki Takenaka ,  Mitsuru Shimizu

发明人： Sumio Tanaka ,  Hiroyuki Takenaka ,  Mitsuru Shimizu

IPC分类号： G01R31/28 ,  G11C11/22 ,  G11C11/401 ,  G11C14/00 ,  G11C29/12 ,  G11C29/34 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C29/34

摘要： A ferroelectric memory has a memory cell screening test circuit connected to bit lines through switching transistors. In screening, at least one word line is selected, and data is simultaneously written in all memory cells connected to this word line. Since data is not restored after the rewrite, all FRAM cells can be screened under the same condition. By this circuit, a memory cell having a write failure according to the imprint characteristics inherent to the ferroelectric memory is screened.

摘要翻译： 铁电存储器具有通过开关晶体管连接到位线的存储单元筛选测试电路。 在筛选中，选择至少一个字线，并且数据被同时写入连接到该字线的所有存储器单元中。 由于重写后数据未恢复，因此可以在相同条件下对所有FRAM单元进行屏蔽。 通过该电路，屏蔽具有根据铁电存储器固有的印记特性的写入故障的存储单元。

公开(公告)号：US5892706A

公开(公告)日：1999-04-06

申请号：US18693

申请日：1998-02-04

申请人： Mitsuru Shimizu ,  Sumio Tanaka

发明人： Mitsuru Shimizu ,  Sumio Tanaka

IPC分类号： G11C5/14 ,  G11C11/22

CPC分类号： G11C5/14 ,  G11C11/22

摘要： Circuitry within a ferroelectric memory prevents inversion of the polarization of ferroelectric memory cells caused by a power on reset signal to avoid corruption of data stored therein. A ferroelectric memory includes a memory cell array, a plurality of word lines commonly connected to the gates of the cell transistors in the same row, a plurality of plate lines commonly connected to the plates of the cell capacitors in the same row, a plurality of bit lines commonly connected to one end of the cell transistors in the same row, and a power on reset circuit for generating a power on reset signal of a predetermined level for a predetermined period of time after the power supply is turned on. An erroneous programming prevention circuit within the memory includes a plurality of switching transistors connected between all of the bit lines and plate lines and a plurality of nodes at a predetermined potential. The switching transistors are controlled by the power on reset signal so that they are on for a predetermined period of time.

摘要翻译： 铁电存储器内的电路防止由上电复位信号引起的铁电存储器单元极化的反转，以避免存储在其中的数据的损坏。 铁电存储器包括存储单元阵列，通常连接到同一行中的单元晶体管的栅极的多个字线，多个板线，共同连接到同一行中的单元电容器的板，多个 通常连接到同一行中的单元晶体管的一端的位线，以及在电源接通之后的预定时间段内产生预定电平的上电复位信号的上电复位电路。 存储器内的错误编程防止电路包括连接在所有位线和板线之间的多个开关晶体管和预定电位的多个节点。 开关晶体管由上电复位信号控制，使得它们在预定时间段内导通。

公开(公告)号：US5943256A

公开(公告)日：1999-08-24

申请号：US2391

申请日：1998-01-02

申请人： Mitsuru Shimizu ,  Sumio Tanaka

发明人： Mitsuru Shimizu ,  Sumio Tanaka

IPC分类号： G11C14/00 ,  G11C11/22 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C11/22

摘要： A nonvolatile ferroelectric memory comprises a memory cell array having memory cells arranged as a matrix array and each including a charge transfer transistor having a source or drain region connected to a bit line and a gate connected to a word line and a ferroelectric capacitor for information storage having one electrode connected to a plate line and the other electrode connected to the drain or source region of the charge transfer transistor. A first dummy line is arranged outside a bit line formed at an end of the memory cell array and second dummy bit lines are arranged between the bit line at the end of the memory cell array and the first dummy bit line. Dummy memory cells are connected to the second dummy bit line and have the same in configuration and size as the memory cells connected to the bit line.

摘要翻译： 非易失性铁电存储器包括存储单元阵列，其具有排列成矩阵阵列的存储单元，每个存储单元包括电荷转移晶体管，该电荷转移晶体管具有连接到位线的源极或漏极区域以及连接到字线的栅极和用于信息存储的铁电电容器 具有连接到板线的一个电极和连接到电荷转移晶体管的漏极或源极区域的另一个电极。 第一虚拟线被布置在形成于存储单元阵列的端部的位线之外，并且第二虚拟位线被布置在存储单元阵列的末端的位线和第一虚拟位线之间。 虚拟存储器单元连接到第二虚位线，并且具有与连接到位线的存储单元相同的配置和大小。

公开(公告)号：US5798964A

公开(公告)日：1998-08-25

申请号：US518440

申请日：1995-08-23

申请人： Mitsuru Shimizu ,  Sumio Tanaka

发明人： Mitsuru Shimizu ,  Sumio Tanaka

IPC分类号： G11C5/14 ,  G11C11/22

CPC分类号： G11C5/14 ,  G11C11/22

摘要： Circuitry within a ferroelectric memory prevents inversion of the polarization of ferroelectric memory cells caused by a power on reset signal to avoid corruption of data stored therein. A ferroelectric memory includes a memory cell array, a plurality of word lines commonly connected to the gates of the cell transistors in the same row, a plurality of plate lines commonly connected to the plates of the cell capacitors in the same row, a plurality of bit lines commonly connected to one end of the cell transistors in the same row, and a power on reset circuit for generating a power on reset signal of a predetermined level for a predetermined period of time after the power supply is turned on. An erroneous programming prevention circuit within the memory includes a plurality of switching transistors connected between all of the bit lines and plate lines and a plurality of nodes at a predetermined potential. The switching transistors are controlled by the power on reset signal so that they are on for a predetermined period of time.

摘要翻译： 铁电存储器内的电路防止由上电复位信号引起的铁电存储器单元极化的反转，以避免存储在其中的数据的损坏。 铁电存储器包括存储单元阵列，通常连接到同一行中的单元晶体管的栅极的多个字线，多个板线，共同连接到同一行中的单元电容器的板，多个 通常连接到同一行中的单元晶体管的一端的位线，以及在电源接通之后的预定时间段内产生预定电平的上电复位信号的上电复位电路。 存储器内的错误编程防止电路包括连接在所有位线和板线之间的多个开关晶体管和预定电位的多个节点。 开关晶体管由上电复位信号控制，使得它们在预定时间段内导通。

公开(公告)号：US5949109A

公开(公告)日：1999-09-07

申请号：US790804

申请日：1997-01-30

申请人： Mitsuru Shimizu ,  Syuso Fujii ,  Kenji Numata ,  Masaharu Wada

发明人： Mitsuru Shimizu ,  Syuso Fujii ,  Kenji Numata ,  Masaharu Wada

IPC分类号： H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0251

摘要： According to this invention, a well region is formed on a semiconductor substrate. An n.sup.+ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N.sup.+ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p.sup.+ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential. The parasitic transistor is turned on upon electrostatic discharge, and the parasitic diode is turned on when a negative potential for test is applied to the input pad, thereby preventing an erroneous operation of a transistor arranged on the semiconductor substrate.

摘要翻译： 根据本发明，在半导体衬底上形成阱区。 在阱区中形成n +型第一半导体区，并且用于接收外部信号的输入焊盘连接在第一半导体区附近。 该输入焊盘连接到由逆变器电路构成的集成电路的输入电路和用于接收外部信号的外部端子。 在位于第一半导体区域的两侧的阱区中形成N +型第二半导体区域。 对这些第二半导体区域施加接地电位Vss。 在阱区中围绕这些第二半导体区域形成p +型第三半导体区域。 接地电位施加到第三半导体区域。 因此，在输入焊盘和接地电位之间形成由寄生晶体管和寄生二极管形成的并联电路。 寄生晶体管在静电放电时导通，当向输入焊盘施加用于测试的负电位时，寄生二极管导通，从而防止布置在半导体衬底上的晶体管的错误操作。

公开(公告)号：US5142492A

公开(公告)日：1992-08-25

申请号：US591948

申请日：1990-10-02

申请人： Mitsuru Shimizu ,  Syuso Fujii

发明人： Mitsuru Shimizu ,  Syuso Fujii

IPC分类号： G11C11/41 ,  G11C5/02 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  H01L27/10

CPC分类号： G11C8/12 ,  G11C5/025

摘要： A semiconductor memory device is disclosed which comprises a regular row/column memory cell array having blocks obtained by dividing the memory cell array in the column and row directions, a first peripheral circuit irregularly provided between the blocks divided in the column direction, a second peripheral circuit provided between the blocks divided in the row direction and including a first decoder, a third peripheral circuit provided between the first peripheral circuit and the respective block and including a second decoder, and a fourth peripheral circuit provided at the marginal portion of the memory cell array and including bonding pads and input protection circuit.

公开(公告)号：US6074196A

公开(公告)日：2000-06-13

申请号：US138524

申请日：1998-08-24

申请人： Mitsuru Shimizu ,  Yoshihiro Fujita

发明人： Mitsuru Shimizu ,  Yoshihiro Fujita

IPC分类号： B29C45/40 ,  B29C45/43 ,  B29D11/00 ,  G02B3/08

CPC分类号： B29C45/43 ,  B29C45/40 ,  B29D11/00269 ,  G02B3/08 ,  Y10S425/102

摘要： An apparatus for producing a Fresnel plate has a mold assembly comprising movable and stationary molds coupled with each other. The mold assembly includes a Fresnel forming face formed on the inside of the movable mold. Melted resin is injected into the mold assembly for forming the Fresnel plate. At least one movable slit is formed through, and arranged inside, the movable mold along a circle concentric with the Fresnel plate and in intermittent or continuous fashion. The movable slit is used for blowing compressed air toward the Fresnel plate. The slit closely surrounds the center of the Fresnel plate. Ejector pins surround the Fresnel plate outside its Fresnel forming face.

摘要翻译： 一种用于制造菲涅尔板的设备具有包括彼此耦合的可移动和固定模具的模具组件。 模具组件包括形成在可动模具内侧的菲涅耳形成面。 将熔融树脂注入到用于形成菲涅尔板的模具组件中。 沿着与菲涅尔板同心的圆周以间歇或连续的方式形成至少一个可移动的狭缝，并且可移动模具的内部布置在活动模具的内部。 可移动狭缝用于向菲涅耳板吹送压缩空气。 狭缝紧密围绕菲涅耳板的中心。 顶针围绕菲涅耳成形面外的菲涅耳板。

公开(公告)号：US5840352A

公开(公告)日：1998-11-24

申请号：US699639

申请日：1996-08-19

申请人： Mitsuru Shimizu ,  Yoshihiro Fujita

发明人： Mitsuru Shimizu ,  Yoshihiro Fujita

IPC分类号： B29C45/40 ,  B29C45/43 ,  B29D11/00 ,  G02B3/08

CPC分类号： B29C45/43 ,  B29C45/40 ,  B29D11/00269 ,  G02B3/08 ,  Y10S425/102

摘要： An apparatus for producing a Fresnel plate has a mold assembly comprising movable and stationary molds coupled with each other. The mold assembly includes a Fresnel forming face formed on the inside of the movable mold. Melted resin is injected into the mold assembly for forming the Fresnel plate. At least one movable slit is formed through, and arranged inside, the movable mold along a circle concentric with the Fresnel plate and in intermittent or continuous fashion. The movable slit is used for blowing compressed air toward the Fresnel plate. The slit closely surrounds the center of the Fresnel plate. Ejector pins surround the Fresnel plate outside its Fresnel forming face.

公开(公告)号：US5794077A

公开(公告)日：1998-08-11

申请号：US740392

申请日：1996-10-29

申请人： Mitsuru Shimizu ,  Ko Aosaki ,  Michio Cho

发明人： Mitsuru Shimizu ,  Ko Aosaki ,  Michio Cho

IPC分类号： G03B17/52 ,  G03B17/50

CPC分类号： G03B17/52 ,  G03B2219/045

摘要： A single-use instant camera includes a main body, having the taking lens and the shutter mechanism. A film unit containing chamber is formed in the main body, and contains a plurality of instant the film units stacked on one another. The containing chamber is opened toward a rear and has a front wall. An exposure aperture is formed in the front wall, and receives the image-recording portion of the film units, to provide the film units with exposure to light a entered through the taking lens from an object to be photographed. A front cover is disposed in front of the main body to cover the main body. An advancing claw mechanism is disposed between the front cover and the main body, and advances an exposed one of the film units to be exited. A flash device is disposed between the front cover and the main body, and applies illuminating light to the object. A back lid is disposed behind the containing chamber, is engaged with the main body, and closes the containing chamber. A pressure plate is mounted on the back lid, and presses the film units toward the exposure aperture.

摘要翻译： 一次性即时照相机包括具有拍摄镜头和快门机构的主体。 在主体中形成有胶片单元容纳室，并且包含彼此堆叠的多个即时胶片单元。 容纳室朝向后方开口并具有前壁。 在前壁中形成曝光孔，并且接收胶片单元的图像记录部分，以便从被拍摄物体向胶片单元提供通过拍摄镜头进入的光的曝光。 前盖设置在主体的前面以覆盖主体。 前进爪机构设置在前盖和主体之间，并且使被退出的一个胶片单元前进。 闪光装置设置在前盖和主体之间，并且向对象施加照明光。 后盖设置在容纳室的后面，与主体接合并且封闭容纳室。 压板安装在后盖上，并将胶片单元压向曝光孔。