公开(公告)号：US6097622A

公开(公告)日：2000-08-01

申请号：US867792

申请日：1997-06-03

申请人： Mitsuru Shimizu ,  Hiroyuki Takenaka ,  Sumio Tanaka

发明人： Mitsuru Shimizu ,  Hiroyuki Takenaka ,  Sumio Tanaka

IPC分类号： G11C11/22 ,  G11C11/404 ,  G11C14/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C11/22

摘要： A ferroelectric memory having a memory cell array or a plurality of memory cell arrays, word lines, where each memory cell array includes word lines. The memory also includes a plurality of plate lines, where each memory cell array includes some of the plate lines and the word line corresponds with some of the plate lines, a bit line, a word line select circuit for selecting among the word lines, and plurality of plate line select circuits, where each of the plate line select circuit is coupled to an associated plate line.

摘要翻译： 具有存储单元阵列或多个存储单元阵列的铁电存储器，字线，其中每个存储单元阵列包括字线。 存储器还包括多个板线，其中每个存储单元阵列包括一些板线，并且字线对应于一些板线，位线，用于在字线之间选择的字线选择电路和 多个板线选择电路，其中每个板线选择电路耦合到相关的板线。

公开(公告)号：US6046926A

公开(公告)日：2000-04-04

申请号：US170104

申请日：1998-10-13

申请人： Sumio Tanaka ,  Hiroyuki Takenaka ,  Mitsuru Shimizu

发明人： Sumio Tanaka ,  Hiroyuki Takenaka ,  Mitsuru Shimizu

IPC分类号： G01R31/28 ,  G11C11/22 ,  G11C11/401 ,  G11C14/00 ,  G11C29/12 ,  G11C29/34 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C29/34

摘要： A ferroelectric memory has a memory cell screening test circuit connected to bit lines through switching transistors. In screening, at least one word line is selected, and data is simultaneously written in all memory cells connected to this word line. Since data is not restored after the rewrite, all FRAM cells can be screened under the same condition. By this circuit, a memory cell having a write failure according to the imprint characteristics inherent to the ferroelectric memory is screened.

摘要翻译： 铁电存储器具有通过开关晶体管连接到位线的存储单元筛选测试电路。 在筛选中，选择至少一个字线，并且数据被同时写入连接到该字线的所有存储器单元中。 由于重写后数据未恢复，因此可以在相同条件下对所有FRAM单元进行屏蔽。 通过该电路，屏蔽具有根据铁电存储器固有的印记特性的写入故障的存储单元。

公开(公告)号：US5943256A

公开(公告)日：1999-08-24

申请号：US2391

申请日：1998-01-02

申请人： Mitsuru Shimizu ,  Sumio Tanaka

发明人： Mitsuru Shimizu ,  Sumio Tanaka

IPC分类号： G11C14/00 ,  G11C11/22 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C11/22

摘要： A nonvolatile ferroelectric memory comprises a memory cell array having memory cells arranged as a matrix array and each including a charge transfer transistor having a source or drain region connected to a bit line and a gate connected to a word line and a ferroelectric capacitor for information storage having one electrode connected to a plate line and the other electrode connected to the drain or source region of the charge transfer transistor. A first dummy line is arranged outside a bit line formed at an end of the memory cell array and second dummy bit lines are arranged between the bit line at the end of the memory cell array and the first dummy bit line. Dummy memory cells are connected to the second dummy bit line and have the same in configuration and size as the memory cells connected to the bit line.

摘要翻译： 非易失性铁电存储器包括存储单元阵列，其具有排列成矩阵阵列的存储单元，每个存储单元包括电荷转移晶体管，该电荷转移晶体管具有连接到位线的源极或漏极区域以及连接到字线的栅极和用于信息存储的铁电电容器 具有连接到板线的一个电极和连接到电荷转移晶体管的漏极或源极区域的另一个电极。 第一虚拟线被布置在形成于存储单元阵列的端部的位线之外，并且第二虚拟位线被布置在存储单元阵列的末端的位线和第一虚拟位线之间。 虚拟存储器单元连接到第二虚位线，并且具有与连接到位线的存储单元相同的配置和大小。

公开(公告)号：US5798964A

公开(公告)日：1998-08-25

申请号：US518440

申请日：1995-08-23

申请人： Mitsuru Shimizu ,  Sumio Tanaka

发明人： Mitsuru Shimizu ,  Sumio Tanaka

IPC分类号： G11C5/14 ,  G11C11/22

CPC分类号： G11C5/14 ,  G11C11/22

摘要： Circuitry within a ferroelectric memory prevents inversion of the polarization of ferroelectric memory cells caused by a power on reset signal to avoid corruption of data stored therein. A ferroelectric memory includes a memory cell array, a plurality of word lines commonly connected to the gates of the cell transistors in the same row, a plurality of plate lines commonly connected to the plates of the cell capacitors in the same row, a plurality of bit lines commonly connected to one end of the cell transistors in the same row, and a power on reset circuit for generating a power on reset signal of a predetermined level for a predetermined period of time after the power supply is turned on. An erroneous programming prevention circuit within the memory includes a plurality of switching transistors connected between all of the bit lines and plate lines and a plurality of nodes at a predetermined potential. The switching transistors are controlled by the power on reset signal so that they are on for a predetermined period of time.

摘要翻译： 铁电存储器内的电路防止由上电复位信号引起的铁电存储器单元极化的反转，以避免存储在其中的数据的损坏。 铁电存储器包括存储单元阵列，通常连接到同一行中的单元晶体管的栅极的多个字线，多个板线，共同连接到同一行中的单元电容器的板，多个 通常连接到同一行中的单元晶体管的一端的位线，以及在电源接通之后的预定时间段内产生预定电平的上电复位信号的上电复位电路。 存储器内的错误编程防止电路包括连接在所有位线和板线之间的多个开关晶体管和预定电位的多个节点。 开关晶体管由上电复位信号控制，使得它们在预定时间段内导通。

公开(公告)号：US5892706A

公开(公告)日：1999-04-06

申请号：US18693

申请日：1998-02-04

申请人： Mitsuru Shimizu ,  Sumio Tanaka

发明人： Mitsuru Shimizu ,  Sumio Tanaka

IPC分类号： G11C5/14 ,  G11C11/22

CPC分类号： G11C5/14 ,  G11C11/22

摘要： Circuitry within a ferroelectric memory prevents inversion of the polarization of ferroelectric memory cells caused by a power on reset signal to avoid corruption of data stored therein. A ferroelectric memory includes a memory cell array, a plurality of word lines commonly connected to the gates of the cell transistors in the same row, a plurality of plate lines commonly connected to the plates of the cell capacitors in the same row, a plurality of bit lines commonly connected to one end of the cell transistors in the same row, and a power on reset circuit for generating a power on reset signal of a predetermined level for a predetermined period of time after the power supply is turned on. An erroneous programming prevention circuit within the memory includes a plurality of switching transistors connected between all of the bit lines and plate lines and a plurality of nodes at a predetermined potential. The switching transistors are controlled by the power on reset signal so that they are on for a predetermined period of time.

摘要翻译： 铁电存储器内的电路防止由上电复位信号引起的铁电存储器单元极化的反转，以避免存储在其中的数据的损坏。 铁电存储器包括存储单元阵列，通常连接到同一行中的单元晶体管的栅极的多个字线，多个板线，共同连接到同一行中的单元电容器的板，多个 通常连接到同一行中的单元晶体管的一端的位线，以及在电源接通之后的预定时间段内产生预定电平的上电复位信号的上电复位电路。 存储器内的错误编程防止电路包括连接在所有位线和板线之间的多个开关晶体管和预定电位的多个节点。 开关晶体管由上电复位信号控制，使得它们在预定时间段内导通。

公开(公告)号：US07295456B2

公开(公告)日：2007-11-13

申请号：US11382098

申请日：2006-05-08

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Sumio Tanaka ,  Yukihito Oowaki ,  Yoshiaki Takeuchi

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.

摘要翻译： 链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线 通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管。 作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值 电压和比较放大。 利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

公开(公告)号：US6166987A

公开(公告)日：2000-12-26

申请号：US443100

申请日：1999-11-18

申请人： Shigeru Atsumi ,  Sumio Tanaka

发明人： Shigeru Atsumi ,  Sumio Tanaka

IPC分类号： G11C17/00 ,  G11C7/00 ,  G11C8/00 ,  G11C8/08 ,  G11C16/06 ,  G11C16/08 ,  G11C16/14 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115

CPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/14

摘要： A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during another modes.

摘要翻译： 提供了一种非易失性半导体存储器件，其中在擦除模式期间将负电压施加到存储单元晶体管的栅电极。 存储器件包括具有连接到字线的N沟道晶体管的行解码器电路。 N沟道晶体管设置在半导体衬底的P型阱区上。 在擦除模式期间，向P型阱区施加负电压，而在其它模式期间施加接地电位。

公开(公告)号：US6111777A

公开(公告)日：2000-08-29

申请号：US401663

申请日：1999-09-23

申请人： Ryu Ogiwara ,  Sumio Tanaka

发明人： Ryu Ogiwara ,  Sumio Tanaka

IPC分类号： G11C14/00 ,  G11C11/22 ,  H01L27/10

CPC分类号： G11C11/22

摘要： A dummy cell is provided in every column and consists of a dummy capacitor and two transistors. When the charge of the ferroelectric capacitor is released to one of a bit line pair, a first dummy word line is selected and charge of the dummy capacitor is released to the other of the bit line pair by way of one of the two transistors. When the charge of the ferroelectric capacitor is released to the other of the bit line pair, a second dummy word line is selected and the charge of the dummy capacitor is released to one of the bit line pair by way of the other one of the two transistors. When either one of the first and second dummy word lines is selected the dummy plate driver supplies a clock signal to the dummy capacitor.

摘要翻译： 每个列提供一个虚拟单元，由虚拟电容器和两个晶体管构成。 当铁电电容器的电荷被释放到位线对中的一个时，选择第一虚拟字线，并且通过两个晶体管之一将虚拟电容器的电荷释放到位线对中的另一个。 当铁电电容器的电荷释放到位线对中的另一个时，选择第二虚拟字线，并且虚拟电容器的电荷通过两个位线对中的另一个被释放到位线对中的一个 晶体管。 当选择第一和第二虚拟字线中的任何一个时，虚拟板驱动器向虚拟电容器提供时钟信号。

公开(公告)号：US5875129A

公开(公告)日：1999-02-23

申请号：US744821

申请日：1996-11-06

申请人： Shigeru Atsumi ,  Sumio Tanaka

发明人： Shigeru Atsumi ,  Sumio Tanaka

IPC分类号： H01L21/8247 ,  G11C16/08 ,  G11C16/30 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C16/08 ,  H01L27/105

摘要： In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.

摘要翻译： 在闪速存储器EEPROM中，在P型半导体衬底中形成存储单元MC。 外围晶体管TR形成在N型阱中。 另一个外围晶体管TR形成在P型阱中。 P型阱依次形成N型阱并与衬底电绝缘。 基板通常设置有金属背部结构，并且其基板电压分别设置为预定电压用于数据擦除，数据存储和数据检索。 通过这样的布置，可以显着地减少在数据擦除期间装载装置的电压应力的水平，以允许对装置实现缩小尺寸和增强的质量。

公开(公告)号：US5265061A

公开(公告)日：1993-11-23

申请号：US943145

申请日：1992-09-10

申请人： Sumio Tanaka

发明人： Sumio Tanaka

IPC分类号： G11C7/14 ,  G11C17/12 ,  G11C7/00 ,  G11C11/40 ,  H03K19/003 ,  H03K19/0175

CPC分类号： G11C17/12 ,  G11C7/14

摘要： A semiconductor non-volatile memory device having non-volatile memory cells for storing binary data, a plurality of column lines respectively connected to the plurality of memory cells and a plurality of row lines respectively connected to the plurality of memory cells comprising a plurality of dummy cells, having the same structure as the memory cells, respectively connected to the column lines and arranged to be set in an ON state upon being selected, a dummy row line connected to the plurality of dummy cells, a dummy row line selector for selecting the dummy row line for a predetermined period in response to a chip selection signal for selecting the memory device. Therefore, since the dummy row line is selected for the predetermined period before the memory device is selected by a computer system or the like, each of the column lines is set at a ground potential by a dummy memory cell set in an ON state. During a transition from the non-selected state to a selected state of the memory device, in synchronism with the transition from the non-selected state to the selected state of a target memory cell in a plurality of memory cells, the state of a dummy cell connected to the target memory cell transits from the selected state to the non-selected state.

摘要翻译： 一种具有用于存储二进制数据的非易失性存储单元的半导体非易失性存储器件，分别连接到多个存储器单元的多个列线以及分别连接到多个存储器单元的多个行线，包括多个虚拟 单元，具有与存储单元相同的结构，分别连接到列线并被布置为在选择时被设置为ON状态，连接到多个虚设单元的虚拟行线，用于选择 响应于用于选择存储器件的芯片选择信号，预定周期的虚拟行线。 因此，由于在通过计算机系统等选择存储器件之前的预定时段内选择了虚拟行线，所以通过设置在ON状态的虚拟存储器单元将每条列线设置为接地电位。 在从非选择状态到存储器件的选择状态的转变期间，与从多个存储器单元中的目标存储器单元从未选择状态到选定状态的转换同步，虚拟的状态 连接到目标存储器单元的单元从所选状态转换到未选择状态。