公开(公告)号：US08552893B1

公开(公告)日：2013-10-08

申请号：US13289806

申请日：2011-11-04

申请人： Mohit Sood ,  Michael Allan Kost

发明人： Mohit Sood ,  Michael Allan Kost

IPC分类号： H03M3/00

CPC分类号： H02M3/157 ,  H02M1/4225 ,  H02M2001/0012 ,  H03M3/476 ,  Y02B70/126

摘要： A control system provides a control signal to a nonlinear plant that generates a response signal responsive to the control signal. The control system includes a detector that detects a predetermined value of a plant quantity, valley switching logic, coupled to the detector, to change a state of a plant switch when the plant quantity is minimized, and a pulse-width modulator, coupled to the valley switching logic, to generate a control signal that controls the plant switch. The valley switching logic includes a nonlinear delta-sigma modulator that compensates for an error in a plant response signal by adjusting the duration of an on-time of a plant switch to cause an average value of the plant response signal to converge toward a target signal value.

摘要翻译： 控制系统向非线性设备提供响应于控制信号产生响应信号的控制信号。 所述控制系统包括检测器，所述检测器检测耦合到所述检测器的植物数量的预定值，谷底切换逻辑，以在植物数量最小化时改变植物开关的状态;以及脉冲宽度调制器， 谷切换逻辑，以产生控制工厂开关的控制信号。 谷切换逻辑包括非线性Δ-Σ调制器，其通过调整工厂开关的接通时间来补偿工厂响应信号中的误差，以使工厂响应信号的平均值朝向目标信号收敛 值。

公开(公告)号：US08536799B1

公开(公告)日：2013-09-17

申请号：US13077483

申请日：2011-03-31

申请人： Robert T. Grisamore ,  Firas S. Azrai ,  Mohit Sood ,  John L. Melanson ,  Eric J. King ,  Jean-Charles Pina

发明人： Robert T. Grisamore ,  Firas S. Azrai ,  Mohit Sood ,  John L. Melanson ,  Eric J. King ,  Jean-Charles Pina

IPC分类号： H05B37/02

CPC分类号： H05B33/0815 ,  G01R19/0046 ,  H05B33/0848 ,  H05B37/0218 ,  H05B37/0263 ,  Y02B20/346

摘要： In at least one embodiment, a lighting system receives an input signal, such as a supply voltage, that can be affected by a dimmer. The supply voltage can be affected by a dimmer when, for example, a dimmer phase cut (i.e. chopped) the supply voltage. A dimmer detection system of the lighting system determines if a dimmer is affecting the supply voltage. In at least one embodiment, the dimmer detection system also determines a type of the dimmer, such as detecting if the dimmer is a leading edge or trailing edge dimmer. In at least one embodiment, the dimmer detection system provides dimmer type data to one or more other circuits such as a switching power converter controller. The one or more other circuits utilize the dimmer type data to affect their operation.

公开(公告)号：US20160181222A1

公开(公告)日：2016-06-23

申请号：US14581280

申请日：2014-12-23

申请人： Mohit Sood ,  Wei Tan ,  George F. Robinson ,  Hin Huat Teoh ,  Tean Wee Ong ,  Ha Ong Wong ,  Boon Yee Ee ,  Kok Beng Hong

发明人： Mohit Sood ,  Wei Tan ,  George F. Robinson ,  Hin Huat Teoh ,  Tean Wee Ong ,  Ha Ong Wong ,  Boon Yee Ee ,  Kok Beng Hong

IPC分类号： H01L23/00 ,  B23K3/06

CPC分类号： H01L24/11 ,  B23K3/0623 ,  H01L21/4853 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/742 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/11436 ,  H01L2224/131 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2924/00012

摘要： Embodiments of the present disclosure are directed toward a pickhead for solder ball placement on an integrated circuit (IC) package, and associated systems and techniques. The pickhead may include a body having a bottom surface that defines a bottom plane of the pickhead. The pickhead may further include a plurality of cavities in the bottom surface to hold respective solder balls to be placed on the IC package. Individual cavities of the plurality of cavities may be recessed from the bottom surface by different recess amounts to provide different extensions of the solder balls with respect to the bottom plane. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及用于在集成电路（IC）封装上的焊球放置的拾取头以及相关联的系统和技术。 拾取头可以包括具有限定拾取头的底平面的底表面的主体。 拾取头还可以包括底表面中的多个空腔，以保持放置在IC封装上的各个焊球。 多个空腔中的各个空腔可以从底表面凹入不同的凹槽，以提供焊球相对于底平面的不同延伸。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09178415B1

公开(公告)日：2015-11-03

申请号：US12751949

申请日：2010-03-31

申请人： Michael A. Kost ,  John L. Melanson ,  Rahul Singh ,  Mohit Sood ,  Zhaohui He

发明人： Michael A. Kost ,  John L. Melanson ,  Rahul Singh ,  Mohit Sood ,  Zhaohui He

IPC分类号： H02M1/00 ,  H02M3/00 ,  H02M3/156

CPC分类号： H02M3/157 ,  H02M1/00 ,  H02M1/32 ,  H02M3/00 ,  H02M3/156 ,  H02M2001/0009

摘要： A power control system includes a switching power converter and a controller. The controller is configured to detect an over-current condition of an inductor current in the switching power converter using at least one non-inductor-current signal. In at least one embodiment, the switching power converter does not have a resistor or resistor network to sense the inductor current. In at least one embodiment, the controller indirectly determines a state of the inductor current using at least one non-inductor-current signal. Potentially damaging inductor current values that are, for example, greater than a normal maximum value or at a value that causes a discontinuous conduction mode system to operate in continuous conduction mode represent exemplary inductor over-current conditions addressed by one embodiment of the power control system.

摘要翻译： 电力控制系统包括开关电力转换器和控制器。 控制器被配置为使用至少一个非电感器电流信号来检测开关功率转换器中的电感器电流的过电流状态。 在至少一个实施例中，开关功率转换器不具有用于感测电感器电流的电阻器或电阻器网络。 在至少一个实施例中，控制器使用至少一个非电感器电流信号间接地确定电感器电流的状态。 例如，大于正常最大值或导致不连续导通模式系统在连续导通模式下工作的值的电位器电流值可能会受到损害，表示电力系统的一个实施例所解决的示例性电感器过电流状况 。

公开(公告)号：US07515076B1

公开(公告)日：2009-04-07

申请号：US11864876

申请日：2007-09-28

申请人： Rahul Singh ,  Prashanth Drakshapalli ,  Jie Fang ,  Edwin De Angel ,  Mohit Sood

发明人： Rahul Singh ,  Prashanth Drakshapalli ,  Jie Fang ,  Edwin De Angel ,  Mohit Sood

IPC分类号： H03M1/00

CPC分类号： H03M3/376 ,  H03M3/458

摘要： A method and apparatus for reducing switching noise in a system-on-chip (SoC) integrated circuit including an analog to digital converter (ADC) provides for reduced noise in the ADC conversions. Sampling circuits of the ADC are operated by sampling clock signals and digital circuits and other noise-generating circuits such as power converters, are operated by digital circuit clock signals. Both sets of clock signals are derived from the same master clock by a clock generator circuit, but an offset is applied in the clock generator circuit to move the edges of the digital circuit clock signals away from critical sampling intervals corresponding to edges of the sampling clocks. In one embodiment, the offset is applied by a processor core that forms part of the digital circuits by setting a value in the clock generator, which the clock generator then loads into the divider after halting the clock to the digital circuits.

摘要翻译： 包括模数转换器（ADC）在内的片上系统（SoC）集成电路中降低开关噪声的方法和装置提供了ADC转换中降低的噪声。 ADC的采样电路通过采样时钟信号进行操作，数字电路和其他噪声发生电路（如电源转换器）由数字电路时钟信号进行操作。 这两组时钟信号由时钟发生器电路从相同的主时钟导出，但是在时钟发生器电路中施加偏移以使数字电路时钟信号的边缘远离对应于采样时钟的边缘的关键采样间隔 。 在一个实施例中，通过设置时钟发生器中的值来构成数字电路的一部分的处理器内核施加偏移，时钟发生器在暂停数字电路的时钟之后将其加载到分频器中。