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33 条记录 (耗时 0.018 秒)

    Method of forming fine interconnection for semiconductor devices
    2.
    发明授权
    Method of forming fine interconnection for semiconductor devices 有权

    公开(公告)号：US10262862B1

    公开(公告)日：2019-04-16

    申请号：US15894095

    申请日：2018-02-12

    申请人： NANYA TECHNOLOGY CORPORATION

    发明人： Chiang-Lin Shih ,  Shing-Yih Shih

    IPC分类号： H01L21/311 ,  H01L21/033 ,  H01L21/28 ,  H01L21/768 ,  H01L21/762

    摘要： The present disclosure provides a method of forming fine interconnection for semiconductor devices. The method includes the following steps: A substrate is provided. A first core layer is formed over the substrate. The first core layer includes a base portion, a plurality of extending line portions extending from the base portion along a first direction, and a plurality of isolated line portions isolated from the base portion. Subsequently, a spacer is formed on the sidewalls of the first core layer. A second core layer is then formed to over the substrate. The second core layer includes a plurality of surrounding line portions surrounding the plurality of isolated line portions, and includes a plurality of enclosed line portions enclosed by the plurality of extending line portions. The spacer is removed to form a plurality of openings between the first core layer and the second core layer. The first core layer and the second core layer are alternately arranged along a second direction perpendicular to the first direction after removing the spacer.

    Method for fabricating semiconductor device with protruding contact
    4.
    发明授权
    Method for fabricating semiconductor device with protruding contact 有权

    公开(公告)号：US11574911B2

    公开(公告)日：2023-02-07

    申请号：US17544663

    申请日：2021-12-07

    申请人： NANYA TECHNOLOGY CORPORATION

    发明人： Chiang-Lin Shih ,  Chih-Hung Chen ,  Szu-Yao Chang

    IPC分类号： H01L27/108

    摘要： The present application discloses a method for fabricating a semiconductor device with a protruding contact. The method includes providing a substrate; forming a bit line structure on the substrate; forming a capacitor contact structure next to the bit line structure; recessing a top surface of the bit line structure; and forming a landing pad layer covering a portion of a top surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

    Bonding pad, semiconductor structure, and method of manufacturing semiconductor structure
    6.
    发明授权
    Bonding pad, semiconductor structure, and method of manufacturing semiconductor structure 有权

    公开(公告)号：US10734338B2

    公开(公告)日：2020-08-04

    申请号：US16268954

    申请日：2019-02-06

    申请人： NANYA TECHNOLOGY CORPORATION

    发明人： Pei-Jhen Wu ,  Chiang-Lin Shih ,  Hsih-Yang Chiu

    IPC分类号： H01L23/52 ,  H01L23/00 ,  H01L23/522

    摘要： The present disclosure relates to a multi-ring bonding pad, a semiconductor structure having the multi-ring bonding pad, and a method of manufacturing the semiconductor structure. The bonding pad includes an inner ring member, an outer ring member, and multiple bridge members. The inner ring member has a pair of first inner edges opposite to each other, a pair of second inner edges opposite to each other, and multiple third inner edges for connecting the first inner edges to the second inner edges. The outer ring member surrounds the inner ring member and has a pair of first outer edges opposite to each other, a pair of second outer edges opposite to each other, and multiple third outer edges for connecting the first outer edges to the second outer edges. The bridge members are disposed between the inner ring member and the outer ring member for connecting the inner ring member to the outer ring member.

    Method for manufacturing semiconductor device
    8.
    发明授权
    Method for manufacturing semiconductor device 有权

    公开(公告)号：US11699635B2

    公开(公告)日：2023-07-11

    申请号：US17495250

    申请日：2021-10-06

    申请人： NANYA TECHNOLOGY CORPORATION

    发明人： Chiang-Lin Shih ,  Pei-Jhen Wu

    IPC分类号： H01L23/48 ,  H01L23/00

    CPC分类号： H01L23/481 ,  H01L24/17 ,  H01L24/33

    摘要： A method for manufacturing a semiconductor device includes preparing a first group of wafers having a plurality of first semiconductor dies embedded in a first photosensitive material layer; forming a plurality of first through vias in the first photosensitive material layer; attaching at least two of the first group of wafers using a first adhesive layer to form a first structure; preparing a second group of wafers having a plurality of second semiconductor dies embedded in a second photosensitive material layer; forming a plurality of second through vias in the second photosensitive material layer; attaching at least two of the second group of wafers using a second adhesive layer to form a second structure; and connecting the first structure to the second structure with a plurality of first metal bumps.

    Integrated circuit device and manufacturing method thereof
    10.
    发明授权
    Integrated circuit device and manufacturing method thereof 有权

    公开(公告)号：US11374009B2

    公开(公告)日：2022-06-28

    申请号：US17070938

    申请日：2020-10-15

    申请人： NANYA TECHNOLOGY CORPORATION

    发明人： Chiang-Lin Shih ,  Yu-Ting Lin

    IPC分类号： H01L27/108 ,  G11C5/06 ,  G11C11/407

    摘要： A DRAM including a silicon substrate, buried word lines, and active areas is provided. The silicon substrate has a carrier surface. The buried word lines are buried in the silicon substrate. The active areas are located on the carrier surface. The buried word lines intersect the active area. Each of the buried word lines has a first width in one of the active area, and has a second width outside the active areas, and the first width is larger than the second width. A manufacturing method of DRAM is also provided.