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    Quantum device
    1.
    发明授权
    Quantum device 有权

    公开(公告)号：US11805708B2

    公开(公告)日：2023-10-31

    申请号：US17347820

    申请日：2021-06-15

    Applicant: NEC Corporation

    Inventor： Katsumi Kikuchi ,  Akira Miyata ,  Suguru Watanabe ,  Takanori Nishi ,  Hideyuki Satou ,  Kenji Nanba ,  Ayami Yamaguchi

    IPC: H10N60/12 ,  G06N10/00 ,  H10N60/80 ,  H10N69/00

    CPC classification number: H10N60/124 ,  G06N10/00 ,  H10N60/805 ,  H10N69/00

    Abstract: A quantum device according to an example embodiment includes a quantum chip 10, and an interposer 20 on which the quantum chip 10 is mounted, in which the interposer 20 includes a conductive wiring line CL1 electrically connected to the quantum chip 10, a mounting surface 21 of the interposer 20 on which the quantum chip 10 is mounted or an opposite surface 22 opposite to the mounting surface 21 includes a first area AR11 and a second area AR12 different from the first area AR11 as viewed in a direction perpendicular to the mounting surface 21 or the opposite surface 22, the conductive wiring line CL1 is disposed in the first area AR11 on the mounting surface 21 or the opposite surface 22, and a movable member 60 is in contact with the second area AR12 of the interposer 20.

    SUPERCONDUCTING DEVICE
    4.
    发明申请
    SUPERCONDUCTING DEVICE 有权

    公开(公告)号：US20220367780A1

    公开(公告)日：2022-11-17

    申请号：US17741659

    申请日：2022-05-11

    Applicant: NEC Corporation

    Inventor： Kunihiko ISHIHARA ,  Suguru Watanabe ,  Katsumi Kikuchi

    IPC: H01L39/04

    Abstract: A superconducting device according to an example embodiment includes: a superconducting chip; an interposer on which the superconducting chip is mounted; a socket that is arranged to face the interposer and includes a movable pin and a housing supporting the movable pin; and a board that is arranged to face the socket and includes a connector serving as an input/output with respect to the outside. In the board, one end of a terminal of a via hole is electrically connected to one end of a terminal of the movable pin, and a hole diameter of the via hole is smaller than a diameter of a tip portion of the movable pin connected to the via hole.

    Quantum device
    5.
    发明授权
    Quantum device 有权

    公开(公告)号：US12108690B2

    公开(公告)日：2024-10-01

    申请号：US17347784

    申请日：2021-06-15

    Applicant: NEC Corporation

    Inventor： Katsumi Kikuchi ,  Akira Miyata ,  Suguru Watanabe ,  Takanori Nishi ,  Hideyuki Satou ,  Kenji Nanba ,  Ayami Yamaguchi

    IPC: H01L39/04 ,  H01R12/71 ,  H10N60/81 ,  H01R13/24

    CPC classification number: H10N60/815 ,  H01R12/714 ,  H01R13/24

    Abstract: A quantum device capable of securing terminals for external connection is provided. A quantum device according to an example embodiment includes a quantum chip 10, an interposer 20 on which the quantum chip 10 is mounted, and a socket 40 disposed so as to be opposed to the interposer 20, the socket 40 comprising a movable pin 47 and a housing 45 supporting the movable pin 47, in which at least one end of the movable pin 47, which includes the one end and the other end opposite to the one end, is movable relative to the housing 45, the one end being in electrical contact with a terminal of the interposer 20, and the other end is in an electrical contact with a terminal of a board 50 on which a connector 51 is formed, the connector 51 being configured to serve as an external input/output.

    Quantum device and method of manufacturing the same
    6.
    发明授权
    Quantum device and method of manufacturing the same 有权

    公开(公告)号：US11696517B2

    公开(公告)日：2023-07-04

    申请号：US17349281

    申请日：2021-06-16

    Applicant: NEC Corporation

    Inventor： Kenji Nanba ,  Ayami Yamaguchi ,  Akira Miyata ,  Katsumi Kikuchi ,  Suguru Watanabe ,  Takanori Nishi ,  Hideyuki Satou

    IPC: G06N10/00 ,  H10N60/81 ,  H10N60/01

    CPC classification number: H10N60/81 ,  H10N60/01 ,  G06N10/00

    Abstract: A quantum device (100) includes: an interposer (112); a quantum chip (111); and a connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111), in which the connection part (130) includes: a plurality of pillars (131) arranged on a main surface of the interposer (112); and a metal film (132) provided on a surface of the plurality of pillars (131) in such a way that it contacts the wiring layer of the quantum chip (111) and the thickness of the metal film at outer peripheral parts of the tip of each of the plurality of pillars (131) becomes larger than the thickness of the metal film at a center part of the tip of each of the plurality of pillars (131).

    Storage cell control system, storage cell control method, and recording medium
    7.
    发明授权
    Storage cell control system, storage cell control method, and recording medium 有权

    公开(公告)号：US10403936B2

    公开(公告)日：2019-09-03

    申请号：US15542511

    申请日：2016-01-15

    Applicant: NEC Corporation

    Inventor： Kenji Kobayashi ,  Masato Yano ,  Suguru Watanabe ,  Hisato Sakuma ,  Koji Kudo

    IPC: H02J7/00 ,  H01M10/44 ,  H02J3/32 ,  H01M10/42 ,  H01M10/48 ,  H01M10/0525

    Abstract: A storage cell control system configured to perform charge/discharge control for a plurality of storage cells under control based on a power adjustment request from a power system includes: a power storage capacity calculating means configured to calculate a current power storage capacity of the storage cell based on storage cell information of the storage cell; a target power storage capacity setting means configured to set a target power storage capacity in stopping an operation of the storage cell; a capacity degradation speed calculating means configured to calculate a current capacity degradation speed and a target capacity degradation speed with respect to each power storage capacity by applying the current power storage capacity and the target power storage capacity to capacity degradation speed correlation information set in advance; and a power distributing means configured to distribute power to the plurality of storage cells in such a manner that when it is assumed that t is an elapsed time from start of operation, a capacity degradation amount DSOCvaried(t) is a time integral value of a capacity degradation speed in a case where the capacity degradation speed varies according to a power storage capacity, and a capacity degradation amount DSOCfixed(t) is a time integral value of a capacity degradation speed in a case where the capacity degradation speed is fixed regardless of a power storage capacity, a capacity degradation amount minimization condition: a capacity degradation amount DSOCvaried(t)≤a capacity degradation amount DSOCfixed(t) is satisfied.

    Quantum device having quantum chip on interposer in contact with sample stage
    9.
    发明授权
    Quantum device having quantum chip on interposer in contact with sample stage 有权

    公开(公告)号：US12094812B2

    公开(公告)日：2024-09-17

    申请号：US17345426

    申请日：2021-06-11

    Applicant: NEC Corporation

    Inventor： Katsumi Kikuchi ,  Akira Miyata ,  Suguru Watanabe ,  Takanori Nishi ,  Hideyuki Satou ,  Kenji Nanba ,  Ayami Yamaguchi

    IPC: H01L23/498 ,  H10N60/80

    CPC classification number: H01L23/49838 ,  H10N60/805

    Abstract: A quantum device capable of improving a cooling effect while securing the number of terminals is provided. A quantum device according to an example embodiment includes a quantum chip 10, and an interposer 20 on which the quantum chip 10 is mounted, in which the interposer 20 includes a conductive wiring line CL1 electrically connected to the quantum chip 10, and a metal film 70 disposed in a part of the interposer 20 that is in contact with a sample stage 30 having a cooling function, and a mounting surface 21 of the interposer 20 on which the quantum chip 10 is mounted or an opposite surface 22 opposite to the mounting surface 21 includes a first area AR11 and a second area AR12 different from the first area AR11 as viewed in a direction perpendicular to the mounting surface 21 or the opposite surface 22.

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