公开(公告)号：US11871682B2

公开(公告)日：2024-01-09

申请号：US17349180

申请日：2021-06-16

Applicant: NEC Corporation

Inventor： Kenji Nanba ,  Ayami Yamaguchi ,  Akira Miyata ,  Katsumi Kikuchi ,  Suguru Watanabe ,  Takanori Nishi ,  Hideyuki Satou

IPC: H10N60/81 ,  H01L23/498 ,  H01L23/34 ,  H10N60/01 ,  G06N10/00

CPC classification number: H10N60/81 ,  H01L23/34 ,  H01L23/49822 ,  H01L23/49838 ,  H10N60/01 ,  G06N10/00 ,  H01L23/49827 ,  H01L23/49888

Abstract: A quantum device (100) includes: an interposer (112); a quantum chip (111); a first connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111); and a second connection part (140) that is provided on a main surface of the interposer (112) where the first connection part (130) is arranged and is connected to a cooling plate (115).

公开(公告)号：US11798895B2

公开(公告)日：2023-10-24

申请号：US17357233

申请日：2021-06-24

Applicant: NEC Corporation

Inventor： Kenji Nanba ,  Ayami Yamaguchi ,  Akira Miyata ,  Katsumi Kikuchi ,  Suguru Watanabe ,  Takanori Nishi ,  Hideyuki Satou

IPC: H01L23/552 ,  G06N10/40 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L23/49888

Abstract: A quantum device (100) includes an interposer (112), a quantum chip (111) mounted on the interposer (112), and a shield part (150) provided so as to surround a quantum circuit region of the interposer (112) and the quantum chip (111). Accordingly, the quantum device (100) is able to prevent interference in the quantum circuit region due to exogenous noise.

公开(公告)号：US12094812B2

公开(公告)日：2024-09-17

申请号：US17345426

申请日：2021-06-11

Applicant: NEC Corporation

Inventor： Katsumi Kikuchi ,  Akira Miyata ,  Suguru Watanabe ,  Takanori Nishi ,  Hideyuki Satou ,  Kenji Nanba ,  Ayami Yamaguchi

IPC: H01L23/498 ,  H10N60/80

CPC classification number: H01L23/49838 ,  H10N60/805

Abstract: A quantum device capable of improving a cooling effect while securing the number of terminals is provided. A quantum device according to an example embodiment includes a quantum chip 10, and an interposer 20 on which the quantum chip 10 is mounted, in which the interposer 20 includes a conductive wiring line CL1 electrically connected to the quantum chip 10, and a metal film 70 disposed in a part of the interposer 20 that is in contact with a sample stage 30 having a cooling function, and a mounting surface 21 of the interposer 20 on which the quantum chip 10 is mounted or an opposite surface 22 opposite to the mounting surface 21 includes a first area AR11 and a second area AR12 different from the first area AR11 as viewed in a direction perpendicular to the mounting surface 21 or the opposite surface 22.

公开(公告)号：US20220036229A1

公开(公告)日：2022-02-03

申请号：US17375943

申请日：2021-07-14

Applicant: NEC Corporation

Inventor： Tomohiro Yamaji ,  Hideyuki Satou ,  Yoshihito Hashimoto ,  Aiko Uchiyama

IPC: G06N10/00 ,  G06F1/20

Abstract: A quantum device includes a quantum chip and a holder. The holder includes a pedestal, a recess portion formed in a main surface of the pedestal so as to be opposed to the quantum chip, and a suction tube provided such that in the recess portion, a suction opening is positioned in a bottom surface of the quantum chip.

公开(公告)号：US20210408358A1

公开(公告)日：2021-12-30

申请号：US17355528

申请日：2021-06-23

Applicant: NEC Corporation

Inventor： Kenji Nanba ,  Ayami Yamaguchi ,  Akira Miyata ,  Katsumi Kikuchi ,  Suguru Watanabe ,  Takanori Nishi ,  Hideyuki Satou

IPC: H01L39/24 ,  G06N10/00 ,  H01L27/18

Abstract: A quantum device (100) includes: an interposer (112); a quantum chip (111); a first connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111); a predetermined signal line (w1) arranged in the wiring layer of the quantum chip (111); first shield wires (ws1) arranged in the wiring layer of the quantum chip (111) along the predetermined signal line (w1); a second shield wire (ws2) arranged in the wiring layer of the interposer (112); and a second connection part (150) that is provided between the interposer (112) and the quantum chip (111) so as to contact the first shield wires (ws1) and the second shield wire (ws2).

公开(公告)号：US12108690B2

公开(公告)日：2024-10-01

申请号：US17347784

申请日：2021-06-15

Applicant: NEC Corporation

Inventor： Katsumi Kikuchi ,  Akira Miyata ,  Suguru Watanabe ,  Takanori Nishi ,  Hideyuki Satou ,  Kenji Nanba ,  Ayami Yamaguchi

IPC: H01L39/04 ,  H01R12/71 ,  H10N60/81 ,  H01R13/24

CPC classification number: H10N60/815 ,  H01R12/714 ,  H01R13/24

Abstract: A quantum device capable of securing terminals for external connection is provided. A quantum device according to an example embodiment includes a quantum chip 10, an interposer 20 on which the quantum chip 10 is mounted, and a socket 40 disposed so as to be opposed to the interposer 20, the socket 40 comprising a movable pin 47 and a housing 45 supporting the movable pin 47, in which at least one end of the movable pin 47, which includes the one end and the other end opposite to the one end, is movable relative to the housing 45, the one end being in electrical contact with a terminal of the interposer 20, and the other end is in an electrical contact with a terminal of a board 50 on which a connector 51 is formed, the connector 51 being configured to serve as an external input/output.

公开(公告)号：US11696517B2

公开(公告)日：2023-07-04

申请号：US17349281

申请日：2021-06-16

Applicant: NEC Corporation

Inventor： Kenji Nanba ,  Ayami Yamaguchi ,  Akira Miyata ,  Katsumi Kikuchi ,  Suguru Watanabe ,  Takanori Nishi ,  Hideyuki Satou

IPC: G06N10/00 ,  H10N60/81 ,  H10N60/01

CPC classification number: H10N60/81 ,  H10N60/01 ,  G06N10/00

Abstract: A quantum device (100) includes: an interposer (112); a quantum chip (111); and a connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111), in which the connection part (130) includes: a plurality of pillars (131) arranged on a main surface of the interposer (112); and a metal film (132) provided on a surface of the plurality of pillars (131) in such a way that it contacts the wiring layer of the quantum chip (111) and the thickness of the metal film at outer peripheral parts of the tip of each of the plurality of pillars (131) becomes larger than the thickness of the metal film at a center part of the tip of each of the plurality of pillars (131).

公开(公告)号：US11805708B2

公开(公告)日：2023-10-31

申请号：US17347820

申请日：2021-06-15

Applicant: NEC Corporation

Inventor： Katsumi Kikuchi ,  Akira Miyata ,  Suguru Watanabe ,  Takanori Nishi ,  Hideyuki Satou ,  Kenji Nanba ,  Ayami Yamaguchi

IPC: H10N60/12 ,  G06N10/00 ,  H10N60/80 ,  H10N69/00

CPC classification number: H10N60/124 ,  G06N10/00 ,  H10N60/805 ,  H10N69/00

Abstract: A quantum device according to an example embodiment includes a quantum chip 10, and an interposer 20 on which the quantum chip 10 is mounted, in which the interposer 20 includes a conductive wiring line CL1 electrically connected to the quantum chip 10, a mounting surface 21 of the interposer 20 on which the quantum chip 10 is mounted or an opposite surface 22 opposite to the mounting surface 21 includes a first area AR11 and a second area AR12 different from the first area AR11 as viewed in a direction perpendicular to the mounting surface 21 or the opposite surface 22, the conductive wiring line CL1 is disposed in the first area AR11 on the mounting surface 21 or the opposite surface 22, and a movable member 60 is in contact with the second area AR12 of the interposer 20.

公开(公告)号：US11983603B2

公开(公告)日：2024-05-14

申请号：US17375943

申请日：2021-07-14

Applicant: NEC Corporation

Inventor： Tomohiro Yamaji ,  Hideyuki Satou ,  Yoshihito Hashimoto ,  Aiko Uchiyama

IPC: G06N10/00 ,  G06F1/20

CPC classification number: G06N10/00 ,  G06F1/20

Abstract: A quantum device includes a quantum chip and a holder. The holder includes a pedestal, a recess portion formed in a main surface of the pedestal so as to be opposed to the quantum chip, and a suction tube provided such that in the recess portion, a suction opening is positioned in a bottom surface of the quantum chip.

公开(公告)号：US11981568B2

公开(公告)日：2024-05-14

申请号：US17426224

申请日：2020-01-27

Applicant: NEC Corporation

Inventor： Ryota Yuge ,  Hideyuki Satou

IPC: C01B32/18 ,  B01J19/12 ,  B01J35/40 ,  B01J35/50

CPC classification number: C01B32/18 ,  B01J19/121 ,  B01J35/40 ,  B01J35/50 ,  C01B2204/22 ,  C01B2204/32 ,  C01P2004/03 ,  C01P2004/04

Abstract: An object of the present invention is to provide a member and a method for producing a fibrous carbon nanohorn aggregate with high efficiency. According to an embodiment of the present invention, there is provided a carbon nanohorn aggregate production member for producing a fibrous carbon nanohorn aggregate in which single-walled carbon nanohorns are aggregated radially and are connected in a fibrous form, comprising: a target fixing jig having a target housing section on an upper surface which has a partition and is capable of mounting a plurality of rod-shaped catalyst-containing carbon targets without making a mutual contact, and a jig guide for movement on a side surface; a jig for target fixing jig movement which is slidably engaged with the jig guide for movement; and a target fixing jig guide which is inclined downward, and is equipped with a guide rail which is adapted to an arrangement of the plurality of rod-shaped catalyst-containing carbon targets, wherein the target fixing jig is slidably engaged with the guide rail, and moves in a downward direction by a weight thereof and in a transverse direction along the guide rail by the jig for target fixing jig movement.