公开(公告)号：US20140380338A1

公开(公告)日：2014-12-25

申请号：US13926089

申请日：2013-06-25

申请人： LEV MAKOVSKY ,  ZEEV SPERBER ,  EFRAIM ROTEM ,  NIR ROSENZWEIG ,  STANISLAV SHWARTSMAN ,  RAANAN SADE ,  IGOR YANOVER ,  GAVRI BERGER ,  TOMER WEINER ,  RON GABOR

发明人： LEV MAKOVSKY ,  ZEEV SPERBER ,  EFRAIM ROTEM ,  NIR ROSENZWEIG ,  STANISLAV SHWARTSMAN ,  RAANAN SADE ,  IGOR YANOVER ,  GAVRI BERGER ,  TOMER WEINER ,  RON GABOR

IPC分类号： G06F9/54

CPC分类号： G06F9/542 ,  G06F1/3206 ,  G06F9/30 ,  G06F9/4856 ,  Y02D10/24 ,  Y02D10/32

摘要： In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to determine a first event count associated with events of a first type that have occurred since a start of a first defined interval. The first core also includes a second event counter to determine a second event count associated with events of a second type that have occurred since the start of the first defined interval, and stall logic to stall execution of operations including at least first operations associated with events of the first type, until the first defined interval is expired responsive to the first event count exceeding a first combination threshold concurrently with the second event count exceeding a second combination threshold. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器至少包括第一核。 第一核心包括执行操作的执行逻辑，以及第一事件计数器，用于确定与自第一定义间隔开始以来已经发生的第一类型的事件相关联的第一事件计数。 第一核心还包括第二事件计数器，用于确定与自第一定义间隔开始以来已经发生的第二类型的事件相关联的第二事件计数，以及停止逻辑以停止包括至少与事件相关联的第一操作的操作的执行 直到第一定义间隔响应于超过第一组合阈值的第一事件计数而超过第二事件计数超过第二组合阈值。 描述和要求保护其他实施例。

公开(公告)号：US20140317422A1

公开(公告)日：2014-10-23

申请号：US13865463

申请日：2013-04-18

申请人： NIR ROSENZWEIG ,  ZEEV SPERBER ,  EFRAIM ROTEM

发明人： NIR ROSENZWEIG ,  ZEEV SPERBER ,  EFRAIM ROTEM

IPC分类号： G06F1/28

CPC分类号： G06F1/3206 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/3836 ,  G06F9/3869 ,  Y02D10/126 ,  Y02D10/172

摘要： In an embodiment, a processor includes at least one core. The at least one core includes an execution unit and a current protection (IccP) controller. The IccP controller may receive instruction width information associated with one or more instructions of an instruction queue prior to execution of the instructions by the execution unit. The IccP controller may determine an anticipated highest current level (Icc) for the at least one core based on the instruction width information. The IccP controller may generate a request for a first license for the at least one core that is associated with the Icc. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括至少一个核。 至少一个核心包括执行单元和电流保护（IccP）控制器。 IccP控制器可以在由执行单元执行指令之前接收与指令队列的一个或多个指令相关联的指令宽度信息。 IccP控制器可以基于指令宽度信息确定至少一个核心的预期最高电流电平（Icc）。 IccP控制器可以产生对于与Icc相关联的至少一个核心的第一许可证的请求。 描述和要求保护其他实施例。

公开(公告)号：US20180095520A1

公开(公告)日：2018-04-05

申请号：US15281806

申请日：2016-09-30

申请人： DORON RAJWAN ,  EFRAIM ROTEM ,  AVINASH N. ANANTHAKRISHNAN ,  ANKUSH VARMA ,  ASSAF GANOR ,  NIR ROSENZWEIG ,  DAVID M. PAWLOWSKI ,  ARIK GIHON ,  NADAV SHULMAN

发明人： DORON RAJWAN ,  EFRAIM ROTEM ,  AVINASH N. ANANTHAKRISHNAN ,  ANKUSH VARMA ,  ASSAF GANOR ,  NIR ROSENZWEIG ,  DAVID M. PAWLOWSKI ,  ARIK GIHON ,  NADAV SHULMAN

IPC分类号： G06F1/32

CPC分类号： G06F1/3296 ,  G06F1/28 ,  Y02D10/172

摘要： In an embodiment, a processor includes a power control unit and a plurality of components. A first component of the plurality of components is to receive a power input from a power supply device. The power control unit is to: determine a received voltage at a power input terminal of the first component; determine a voltage difference between the received voltage of the first component and a reliability goal voltage of the first component; determine a running average value based on the voltage difference; and adjust a supply voltage of the power supply device based on the running average value. Other embodiments are described and claimed.

公开(公告)号：US20150091550A1

公开(公告)日：2015-04-02

申请号：US14040346

申请日：2013-09-27

申请人： EFRAIM ROTEM ,  NIR ROSENZWEIG ,  JEFFREY A. CARLSON ,  PHILIP R. LEHWALDER ,  NADAV SHULMAN ,  DORON RAJWAN

发明人： EFRAIM ROTEM ,  NIR ROSENZWEIG ,  JEFFREY A. CARLSON ,  PHILIP R. LEHWALDER ,  NADAV SHULMAN ,  DORON RAJWAN

IPC分类号： G01R19/252

CPC分类号： G01R31/3648 ,  G01R21/133 ,  G01R22/10 ,  G01R31/3624

摘要： Examples are disclosed for an integrated circuit (IC) device coupled to a battery-operated power supply unit, such as an IC in a mobile computing device or wireless phone, to accurately determine energy usage drawn from the power supply unit under rapidly dynamic circumstances. A current sense signal of a power line from the power supply unit is digitized. The digitized current sense is added to an accumulator at a rate that is approximately proportional to a voltage of the power line from the power supply unit. The accumulator is then outputted and scaled to units relevant to energy measurements. The energy measurement is used to estimate remaining battery life. Triggering the digitization of the current sense signal may be by use of a pulse generation circuit, or by use of an overflow indicator of an accumulator for a digitized voltage sense signal. Other examples are described and claimed.

摘要翻译： 公开了用于耦合到诸如移动计算设备或无线电话中的IC的电池供电单元的集成电路（IC）设备的实例，以在快速动态的情况下精确地确定从电源单元获取的能量使用。 来自电源单元的电力线的电流感测信号被数字化。 数字化电流检测以与来自电源单元的电力线的电压近似成比例的速率被添加到累加器。 然后将累加器输出并缩放到与能量测量相关的单位。 能量测量用于估计剩余电池寿命。 触发电流检测信号的数字化可以通过使用脉冲发生电路，或者通过使用累加器的溢出指示符来进行数字化的电压检测信号。 其他的例子被描述和要求保护。

公开(公告)号：US20140281634A1

公开(公告)日：2014-09-18

申请号：US14211987

申请日：2014-03-14

申请人： EFRAIM ROTEM ,  BENJAMIN J. GOULD ,  JAMES G. HERMERDING, II ,  JORGE P. RODRIGUEZ ,  ALON NAVEH ,  NIR ROSENZWEIG ,  VIJAY S. R. DEGALAHAL

发明人： EFRAIM ROTEM ,  BENJAMIN J. GOULD ,  JAMES G. HERMERDING, II ,  JORGE P. RODRIGUEZ ,  ALON NAVEH ,  NIR ROSENZWEIG ,  VIJAY S. R. DEGALAHAL

IPC分类号： G06F1/32

CPC分类号： G06F1/325 ,  G06F1/3206 ,  Y02D50/20

摘要： Methods and apparatus relating to controlling power consumption by a Power Supply Unit (PSU) during idle state are described. In one embodiment, a power supply unit enters a lower power consumption state (e.g. S9) based on power state information, corresponding to one or more components of the platform, and comparison of a first value (corresponding to a frequency/frequentness of entry into the lower power consumption state) to a first threshold value. Other embodiments are also disclosed and claimed.

摘要翻译： 描述了在空闲状态期间由电源单元（PSU）控制功率消耗的方法和装置。 在一个实施例中，电源单元基于对应于平台的一个或多个组件的功率状态信息进入较低功耗状态（例如S9），并且将第一值（对应于进入的频率/频率 较低功耗状态）变为第一阈值。 还公开并要求保护其他实施例。

公开(公告)号：US20160246359A1

公开(公告)日：2016-08-25

申请号：US15143309

申请日：2016-04-29

申请人： EFRAIM ROTEM ,  OREN LAMDAN ,  ALON NAVEH

发明人： EFRAIM ROTEM ,  OREN LAMDAN ,  ALON NAVEH

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/30083 ,  G06F9/3814 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/602 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172 ,  Y02D50/20

摘要： For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.

摘要翻译： 对于一个公开的实施例，处理器包括多个处理器核心，以可变的性能水平进行操作。 多个处理器核心中的一个可以在与多个处理器核心中的另一个处理器核心可以一次操作的性能水平不同的性能水平上一次操作。 多个处理器核心处于相同的封装中。 处理器的逻辑是为多个处理器核中的一个或多个设置一个或多个操作参数。 处理器的逻辑是监视多个处理器核中的一个或多个的活动。 处理器的逻辑是至少部分地基于所监视的活动来约束多个处理器核心中的一个或多个的功率。 限制功率的逻辑是限制可以设置多个处理器核中的一个或多个的频率。 还公开了其他实施例。

公开(公告)号：US20160018882A1

公开(公告)日：2016-01-21

申请号：US14866874

申请日：2015-09-26

申请人： EFRAIM ROTEM ,  OREN LAMDAN ,  ALON NAVEH

发明人： EFRAIM ROTEM ,  OREN LAMDAN ,  ALON NAVEH

IPC分类号： G06F1/32 ,  G06F9/38 ,  G06F12/08

CPC分类号： G06F1/3287 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/30083 ,  G06F9/3814 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/602 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172 ,  Y02D50/20

摘要： For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.

摘要翻译： 对于一个公开的实施例，处理器包括多个处理器核心，以可变的性能水平进行操作。 多个处理器核心中的一个可以在与多个处理器核心中的另一个处理器核心可以一次操作的性能水平不同的性能水平上一次操作。 多个处理器核心处于相同的封装中。 处理器的逻辑是为多个处理器核中的一个或多个设置一个或多个操作参数。 处理器的逻辑是监视多个处理器核中的一个或多个的活动。 处理器的逻辑是至少部分地基于所监视的活动来约束多个处理器核心中的一个或多个的功率。 限制功率的逻辑是限制可以设置多个处理器核中的一个或多个的频率。 还公开了其他实施例。

公开(公告)号：US20150006829A1

公开(公告)日：2015-01-01

申请号：US13930212

申请日：2013-06-28

申请人： DORON RAJWAN ,  NADAV SHULMAN ,  DORIT SHAPIRA ,  KOSTA LURIA ,  EFRAIM ROTEM

发明人： DORON RAJWAN ,  NADAV SHULMAN ,  DORIT SHAPIRA ,  KOSTA LURIA ,  EFRAIM ROTEM

IPC分类号： G06F11/30

CPC分类号： G06F11/3037 ,  G06F11/3419 ,  G06F11/3476 ,  G06F2201/88

摘要： In an embodiment, a processor includes measurement logic to measure a usage associated with the processor. The processor also includes statistical logic to determine, based on a statistical procedure, whether to provide a permission to record an increase in usage responsive to an indication that the usage has increased by a defined amount. The processor also includes control logic to record the defined increase in usage in non-volatile memory responsive to receipt of the permission to record from the statistical logic. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，处理器包括用于测量与处理器相关联的使用的测量逻辑。 处理器还包括用于基于统计过程来确定是否提供响应于使用已经增加了定义量的指示来记录使用增加的许可的统计逻辑。 处理器还包括控制逻辑，用于响应于从统计逻辑接收到记录的许可而记录在非易失性存储器中的定义的使用增加。 描述和要求保护其他实施例。

公开(公告)号：US20130232368A1

公开(公告)日：2013-09-05

申请号：US13782492

申请日：2013-03-01

申请人： ERIC FETZER ,  REID RIEDLINGER ,  DON SOLTIS ,  WILLIAM BOWHILL ,  SATISH SHRIMALI ,  KRISHNAKANTH SISTLA ,  EFRAIM ROTEM ,  RAKESH KUMAR ,  VIVEK GARG ,  ALON NAVEH ,  LOKESH SHARMA

发明人： ERIC FETZER ,  REID RIEDLINGER ,  DON SOLTIS ,  WILLIAM BOWHILL ,  SATISH SHRIMALI ,  KRISHNAKANTH SISTLA ,  EFRAIM ROTEM ,  RAKESH KUMAR ,  VIVEK GARG ,  ALON NAVEH ,  LOKESH SHARMA

IPC分类号： G06F1/32

CPC分类号： G06F1/3296 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

摘要： A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.

摘要翻译： 处理器可以包括核心和无孔区域。 可以通过控制处理器的Cdyn来控制核心区域消耗的功率，使得Cdyn处于可允许的Cdyn值内，而不管应用程序是否被核心区域处理。 电源管理技术包括测量数字活动因素（DAF），监控架构和数据活动级别，以及通过基于活动级别来限制指令来控制功耗。 作为节流指令的结果，节流可以在第3垂直和热设计点（TDP）中实现。 此外，通过改变提供给无孔区域的参考电压VR和VP，可以减少核心区域处于深功率节省状态时由无孔区域消耗的空闲功率。 结果，可以减少由无孔区域消耗的空闲功率。

公开(公告)号：US20160004296A1

公开(公告)日：2016-01-07

申请号：US14322185

申请日：2014-07-02

申请人： JAWADH HAJ-YIHIA ,  ELIEZER WEISSMANN ,  VIJAY S R DEGALAHAL ,  NADAV SHULMAN ,  TAL KUZI ,  ITAY FRANKO ,  AMIT GUR ,  EFRAIM ROTEM

发明人： JAWADH HAJ-YIHIA ,  ELIEZER WEISSMANN ,  VIJAY S R DEGALAHAL ,  NADAV SHULMAN ,  TAL KUZI ,  ITAY FRANKO ,  AMIT GUR ,  EFRAIM ROTEM

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3243 ,  Y02D10/152 ,  Y02D10/171

摘要： Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

摘要翻译： 描述了与自主C状态机制和计算引擎对准相关的方法和设备，以提高处理器功率效率。 一个实施例基于用于进入和退出包装C状态的能量消耗值，半导体封装在包装C中保持在预先状态的时间量以及一个或多个盈亏平衡时间来确定半导体封装是否应该进入封装C状态 各种封装C状态之间的点。 另一个实施例检测处理器的成像计算单元相对于处理器的一个或多个其它计算单元进入低功耗状态的延迟。 该逻辑使成像计算单元响应于延迟的检测而进入低功耗状态。 还公开并要求保护其他实施例。