公开(公告)号：US20160005679A1

公开(公告)日：2016-01-07

申请号：US14322419

申请日：2014-07-02

Applicant: NXP B.V.

Inventor： Emil Casey Israel ,  Leonardus Antonius Elisabeth van Gemert ,  Roelf Anco Jacob Groenhuis

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/304 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L21/683

CPC classification number: H01L21/304 ,  H01L21/561 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L29/0657 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/48177 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18165 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/20752 ,  H01L2224/85 ,  H01L2924/206

Abstract: Consistent with an example embodiment, there is a method for packaging an integrated circuit (IC) device. The method comprises attaching a lead frame to the carrier tape; the lead frame has an array of device positions on the carrier tape and pad landings surround the device positions for making electrical connections to the plurality of active device die. A plurality of active device die are mounted on the carrier tape within the array of device positions; each said active device die has bond pads, each of said active device die has been subjected to back-grinding to a prescribed thickness and has a solderable conductive surface on its underside. On the bond pads, the plurality of active devices are wire bonded to the pad landings on the lead frame. The lead frame and wire bonded active devices are encapsulated, leaving the solderable die backside and lead frame backside exposed.

Abstract translation: 与示例性实施例一致，存在用于封装集成电路（IC）设备的方法。 该方法包括将引线框架附接到载带上; 引线框架具有载体带上的器件位置阵列，并且围绕着用于与多个有源器件管芯电连接的器件位置的焊盘接地。 多个有源器件管芯安装在器件位置阵列内的载体带上; 每个所述有源器件管芯具有接合焊盘，所述有源器件管芯中的每一个已经经过后研磨至规定厚度，并且在其下侧具有可焊接的导电表面。 在接合焊盘上，多个有源器件被引线接合到引线框架上的焊盘平台上。 引线框架和引线键合有源器件被封装，留下可焊接模具背面和引线框架背面暴露。

公开(公告)号：US20170025334A1

公开(公告)日：2017-01-26

申请号：US14806526

申请日：2015-07-22

Applicant: NXP B.V.

Inventor： Leonardus Antonius Elisabeth van Gemert ,  Tonny Kamphuis ,  Rintje van der Meulen ,  Emil Casey Israel

IPC: H01L23/495 ,  H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/49568 ,  H01L21/4821 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/838 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/8384 ,  H01L2224/92247 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/20752

Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a lead frame array, of a first thickness, with a plurality of die placement areas each die placement area with bond pad landings, the bond bad landings situated about a die placement area on one or multiple sides, the bond pad landings having upper surfaces and opposite lower surfaces, placing a heat sink assembly of a second thickness, having at least two mounting tabs of the first thickness, in each die placement area and attaching the at least two mounting tabs onto corresponding bond pad landings serving as anchor pads, die bonding a device die on the heat sink device assembly, conductively bonding device die bond pads to corresponding bond pad landings, and encapsulating the wire bonded device die, heat sink assembly and lead frame array in a molding compound.

Abstract translation: 与示例性实施例一致，存在制备具有增强散热的集成电路（IC）装置的方法。 该方法包括提供具有第一厚度的引线框架阵列和多个管芯放置区域，每个管芯放置区域都具有接合焊盘着陆部分，所述焊接不良接地位于一侧或多侧上的管芯放置区域周围，接合焊盘着陆 具有上表面和相对的下表面，将具有第二厚度的至少两个第一厚度的安装突片的第二厚度的散热器组件放置在每个管芯放置区域中，并将所述至少两个安装突片附接到用作锚固件的相应接合焊盘平台上 衬垫，将器件裸片焊接在散热器器件组件上，将器件管芯接合焊盘导电地接合到相应的接合焊盘平台上，并将引线接合器件管芯，散热器组件和引线框架阵列封装在模制化合物中。

公开(公告)号：US09263299B2

公开(公告)日：2016-02-16

申请号：US14322656

申请日：2014-07-02

Applicant: NXP B.V.

Inventor： Leonardus Antonius Elisabeth van Gemert ,  Emil Casey Israel

IPC: H01L21/00 ,  H01L21/48 ,  H01L23/495 ,  H01L21/56

CPC classification number: H01L21/4825 ,  H01L21/4842 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49582 ,  H01L24/40 ,  H01L24/97 ,  H01L2224/40095 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/37099

Abstract: In an example embodiment, an integrated circuit (IC) comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a conductive surface. A first set of lead frame clips having upper portions and lower portions, are solder-anchored, on the upper portions, to a first set of bond pads; the lower portions are flush with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The device is encapsulated in a molding compound leaving exposed the conductive surface and underside surfaces of the first and second sets of the lead frame portions.

Abstract translation: 在一个示例性实施例中，集成电路（IC）包括具有顶侧表面和下侧表面的器件管芯，所述顶侧表面具有连接到有源电路元件的接合焊盘，所述底侧表面具有导电 表面。 具有上部和下部的第一组引线框架夹在上部焊接到第一组接合焊盘; 下部与导电表面齐平。 电线被连接到与第一组接合焊盘相对的附加的一组接合焊盘，并且与第一组引线框夹相对的第二组引线框架夹的下引线框架部分下降; 第二组引线框架夹子的下引线框架部分与导电表面齐平。 该装置被封装在模制化合物中，暴露出第一和第二组引线框架部分的导电表面和下表面。

公开(公告)号：US20160005680A1

公开(公告)日：2016-01-07

申请号：US14322553

申请日：2014-07-02

Applicant: NXP B.V.

Inventor： Emil Casey Israel ,  Leonardus Antonius Elisabeth van Gemert ,  Tonny Kamphuis

IPC: H01L23/495 ,  H01L21/82 ,  H01L21/52

CPC classification number: H01L23/49568 ,  H01L21/52 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49548 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a heat sink array having a top-side surface and an under-side surface; the heat sink array has die placement areas on the top-side surface. A plurality of active device die are die bonded onto the die placement areas on the heat sink array. The plurality of active device die are singulated into an individual heat sink device die having a heat sink portion attached to its underside.

Abstract translation: 与示例性实施例一致，存在制备具有增强散热的集成电路（IC）装置的方法。 该方法包括提供具有顶侧表面和下侧表面的散热器阵列; 散热器阵列在顶侧表面具有管芯放置区域。 多个有源器件裸片裸片结合到散热片阵列上的管芯放置区域上。 多个有源器件管芯被分割成具有附接到其下侧的散热器部分的单个散热器器件管芯。

公开(公告)号：US09953903B2

公开(公告)日：2018-04-24

申请号：US14806526

申请日：2015-07-22

Applicant: NXP B.V.

Inventor： Leonardus Antonius Elisabeth van Gemert ,  Tonny Kamphuis ,  Rintje van der Meulen ,  Emil Casey Israel

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/433 ,  H01L21/78 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/49568 ,  H01L21/4821 ,  H01L21/4882 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/838 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/8384 ,  H01L2224/92247 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/20752

Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a lead frame array, of a first thickness, with a plurality of die placement areas each die placement area with bond pad landings, the bond bad landings situated about a die placement area on one or multiple sides, the bond pad landings having upper surfaces and opposite lower surfaces, placing a heat sink assembly of a second thickness, having at least two mounting tabs of the first thickness, in each die placement area and attaching the at least two mounting tabs onto corresponding bond pad landings serving as anchor pads, die bonding a device die on the heat sink device assembly, conductively bonding device die bond pads to corresponding bond pad landings, and encapsulating the wire bonded device die, heat sink assembly and lead frame array in a molding compound.

公开(公告)号：US20160005626A1

公开(公告)日：2016-01-07

申请号：US14322656

申请日：2014-07-02

Applicant: NXP B.V.

Inventor： Leonardus Antonius Elisabeth van Gemert ,  Emil Casey Israel

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/495

CPC classification number: H01L21/4825 ,  H01L21/4842 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49582 ,  H01L24/40 ,  H01L24/97 ,  H01L2224/40095 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/37099

Abstract: In an example embodiment, an integrated circuit (IC) comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a conductive surface. A first set of lead frame clips having upper portions and lower portions, are solder-anchored, on the upper portions, to a first set of bond pads; the lower portions are flush with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The device is encapsulated in a molding compound leaving exposed the conductive surface and underside surfaces of the first and second sets of the lead frame portions.

Abstract translation: 在示例性实施例中，集成电路（IC）包括具有顶侧表面和下侧表面的器件管芯，所述顶侧表面具有连接到有源电路元件的接合焊盘，所述底侧表面具有导电 表面。 具有上部和下部的第一组引线框架夹在上部焊接到第一组接合焊盘; 下部与导电表面齐平。 电线被连接到与第一组接合焊盘相对的附加的一组接合焊盘，并且与第一组引线框架夹相对的第二组引线框架夹的下引线框架部分下降; 第二组引线框架夹子的下引线框架部分与导电表面齐平。 该装置被封装在模制化合物中，暴露出第一和第二组引线框架部分的导电表面和下表面。