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公开(公告)号：US20240203912A1
公开(公告)日：2024-06-20
申请号：US18067788
申请日：2022-12-19
Applicant: NXP USA, Inc.
Inventor： Jeffrey Spencer Roberts , Lu Wang , Fernando A. Santos
IPC: H01L23/66 , H01L21/48 , H01L23/367 , H01L23/373 , H01L23/498 , H01L25/065 , H03F1/02 , H03F3/195
CPC classification number: H01L23/66 , H01L21/4882 , H01L23/3675 , H01L23/3736 , H01L23/49816 , H01L23/49833 , H01L23/49844 , H01L25/0655 , H03F1/0288 , H03F3/195 , H01L24/32 , H01L2223/6611 , H01L2223/6622 , H01L2223/6627 , H01L2223/665 , H01L2223/6655 , H01L2224/32245 , H01L2924/1306 , H01L2924/1421 , H03F2200/451
Abstract: An amplifier module includes a module substrate with a mounting surface, and a thermal dissipation structure that extends through the module substrate. A ground contact of a power transistor die is coupled to a surface of the thermal dissipation structure. Encapsulant material covers the mounting surface of the module substrate and the power transistor die, and a surface of the encapsulant material defines a contact surface of the amplifier module. A ground terminal is embedded within the encapsulant material. The ground terminal has a proximal end coupled to the thermal dissipation structure, and a distal end exposed at the contact surface. The ground terminal is electrically coupled to the ground contact of the power transistor die through the thermal dissipation structure.
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公开(公告)号：US11128269B2
公开(公告)日：2021-09-21
申请号：US16718679
申请日：2019-12-18
Applicant: NXP USA, Inc.
Inventor： Elie A. Maalouf , Yu-Ting David Wu , Lu Wang , Nick Yang
Abstract: An amplifier includes a driver stage amplifier transistor and a final stage amplifier transistor, which are integrated in a semiconductor die. The driver stage amplifier transistor has a driver stage input, a driver stage output, and an output impedance, and the driver stage amplifier transistor is configured to operate using a first bias voltage at the driver stage output. The final stage amplifier transistor has a final stage input, a final stage output, and an input impedance. The final stage input is electrically coupled to the driver stage output. The final stage amplifier transistor is configured to operate using a second bias voltage at the final stage output, and the second bias voltage is at least twice as large as the first bias voltage.
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3.发明授权公开(公告)号：US10903182B1
公开(公告)日：2021-01-26
申请号：US16563743
申请日：2019-09-06
Applicant: NXP USA, INC.
Inventor： Lu Wang , Elie A. Maalouf
Abstract: Embodiments of a method and device are disclosed. In an embodiment, a Doherty amplifier module includes a substrate including a mounting surface, and a carrier amplifier die, a first peaking amplifier die, and a second peaking amplifier die on the mounting surface. The carrier amplifier die includes a first output bond pad that has a first length and a first width. The first peaking amplifier die includes a second output bond pad including a first main pad portion having a second length and a second width and including a first side pad portion having a third length and a third width. At least one of the second width or the third width is greater than the first width. The second peaking amplifier includes a third output bond pad. A first wirebond array is coupled between the third output bond pad and at least the first side pad portion.
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公开(公告)号：US11693029B2
公开(公告)日：2023-07-04
申请号：US17378349
申请日：2021-07-16
Applicant: NXP USA, Inc.
Inventor： Joshua Bennett English , Lu Wang
CPC classification number: G01R1/07335 , G01R31/2808 , G01R1/06766
Abstract: Evaluation board (EVB) assemblies or stacks utilized in tuning electronic modules are disclosed, as are methods for tuning such modules. In embodiments, the module testing assembly includes an EVB and an EVB baseplate. The EVB includes, in turn, an EVB through-port extending from a first EVB side to a second, opposing EVB side; and a module mount region on the first EVB side and extending about a periphery of the EVB through-port. The module mount region is shaped and sized to accommodate installation of a sample electronic module provided in a partially-completed, pre-encapsulated state fabricated in accordance with a separate thermal path electronic module design. A baseplate through-port combines with the EVB through-port to form a tuning access tunnel providing physical access to circuit components of the sample electronic module through the EVB baseplate from the second EVB side when the sample electronic module is installed on the module mount region.
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Patent Agency Ranking
公开(公告)号：US20230014716A1
公开(公告)日：2023-01-19
申请号：US17378349
申请日：2021-07-16
Applicant: NXP USA, Inc.
Inventor： Joshua Bennett English , Lu Wang
Abstract: Evaluation board (EVB) assemblies or stacks utilized in tuning electronic modules are disclosed, as are methods for tuning such modules. In embodiments, the module testing assembly includes an EVB and an EVB baseplate. The EVB includes, in turn, an EVB through-port extending from a first EVB side to a second, opposing EVB side; and a module mount region on the first EVB side and extending about a periphery of the EVB through-port. The module mount region is shaped and sized to accommodate installation of a sample electronic module provided in a partially-completed, pre-encapsulated state fabricated in accordance with a separate thermal path electronic module design. A baseplate through-port combines with the EVB through-port to form a tuning access tunnel providing physical access to circuit components of the sample electronic module through the EVB baseplate from the second EVB side when the sample electronic module is installed on the module mount region.
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公开(公告)号：US11050388B2
公开(公告)日：2021-06-29
申请号：US16563728
申请日：2019-09-06
Applicant: NXP USA, INC.
Inventor： Lu Wang , Elie A. Maalouf , Joseph Staudinger , Jeffrey Kevin Jones
Abstract: Embodiments of a method and a device are disclosed. In an embodiment, a Doherty amplifier module includes a substrate including a mounting surface, and further includes a first amplifier die, a second amplifier die, and a third amplifier die on the mounting surface. The first amplifier die is configured to amplify a first radio frequency (RF) signal along a first signal path, the second amplifier die is configured to amplify a second RF signal along a second signal path, and the third amplifier die is configured to amplify a third RF signal along a third signal path. A side of the first amplifier die including a first output terminal faces a side of the second amplifier die including a second output terminal. The second signal path is parallel to the first signal path, and the third signal path is orthogonal to the first and second signal paths.
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7.发明公开公开(公告)号：US20240186212A1
公开(公告)日：2024-06-06
申请号：US18062087
申请日：2022-12-06
Applicant: NXP USA, Inc.
Inventor： Stephen Reza Hiemstra , Lu Wang , Joshua Bennett English
CPC classification number: H01L23/3675 , H01L23/66 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/072 , H01L25/165 , H03F1/0288 , H03F3/195 , H03F3/604 , H01L2223/6611 , H01L2223/6616 , H01L2223/665 , H01L2223/6655 , H01L2223/6672 , H01L2223/6677 , H01L2224/32245 , H01L2224/48195 , H01L2224/48225 , H01L2224/73265 , H01L2924/1421 , H01L2924/2027 , H01L2924/30107 , H01L2924/30111 , H03F2200/451
Abstract: A power amplifier module includes a module substrate. First and second heat dissipation structures extend through the module substrate, and each has a first surface exposed at a mounting surface of the module substrate, and a second surface exposed at a bottom surface of the module substrate. The first surfaces of the first and second heat dissipation structures are physically separated by a portion of the mounting surface. First and second amplifier dies are coupled to the first surface of the first heat dissipation structure. The first amplifier die includes a first power transistor that functions as a driver amplifier. The second amplifier die includes a second power transistor that functions as a first final amplifier. The third amplifier die is coupled to the first surface of the second heat dissipation structure, and the third amplifier die includes a third power transistor that functions as a second final amplifier.
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公开(公告)号：US11515842B2
公开(公告)日：2022-11-29
申请号：US17071991
申请日：2020-10-15
Applicant: NXP USA, Inc.
Inventor： Lu Wang , Elie A Maalouf
Abstract: Doherty power amplifiers and devices are described with a low voltage driver stage in a carrier-path and a high voltage driver stage in a peaking-path. In an embodiment a Doherty power amplifier has a carrier-path driver stage transistor configured to operate using a first bias voltage at the driver stage output, and a final stage transistor configured to operate using a second bias voltage at the final stage output. A peaking-path driver stage transistor is configured to operate using a third bias voltage at the driver stage output, and a final stage transistor electrically coupled to the driver stage output of the peaking-path driver stage transistor is configured to operate using a fourth bias voltage at the final stage output, wherein the third bias voltage is at least twice as large as the first bias voltage.
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公开(公告)号：US20210194443A1
公开(公告)日：2021-06-24
申请号：US16718679
申请日：2019-12-18
Applicant: NXP USA, Inc.
Inventor： Elie A. Maalouf , Yu-Ting David Wu , Lu Wang , Nick Yang
Abstract: An amplifier includes a driver stage amplifier transistor and a final stage amplifier transistor, which are integrated in a semiconductor die. The driver stage amplifier transistor has a driver stage input, a driver stage output, and an output impedance, and the driver stage amplifier transistor is configured to operate using a first bias voltage at the driver stage output. The final stage amplifier transistor has a final stage input, a final stage output, and an input impedance. The final stage input is electrically coupled to the driver stage output. The final stage amplifier transistor is configured to operate using a second bias voltage at the final stage output, and the second bias voltage is at least twice as large as the first bias voltage.
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