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公开(公告)号：US5799160A
公开(公告)日：1998-08-25
申请号：US669071
申请日：1996-06-24
IPC分类号： G06F13/364 , G06F13/00
CPC分类号： G06F13/364
摘要： Control over bus arbitration within a data processing system between a plurality of bus devices (101, 102) coupled by a bus (103) is performed in a user programmable manner by implementing logic circuitry that is responsive to a user programmable bit within a register (203) so that when the bit is asserted, the bus device (102) is able to maintain control over access to the external bus (103). Such a technique is useful for permitting a processor (201) to maintain mastership of an external bus (103) with respect to a direct memory access device (101) also coupled to the bus (103).
摘要翻译： 在由总线（103）耦合的多个总线设备（101,102）之间的数据处理系统内的总线仲裁的控制以用户可编程的方式通过实现响应于寄存器内的用户可编程位的逻辑电路 203），使得当该位被置位时，总线装置（102）能够保持对对外部总线（103）的访问的控制。 这种技术对于允许处理器（201）相对于也耦合到总线（103）的直接存储器访问设备（101）来维持外部总线（103）的掌握是有用的。
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公开(公告)号：US5890196A
公开(公告)日：1999-03-30
申请号：US623499
申请日：1996-03-28
CPC分类号： G06F13/1663
摘要： An external bus master (205) accesses a DRAM (207) using a memory controller (804) internal to a data processor (3) without the use of external multiplexers or any other external circuitry. The need for external multiplexers and even a dedicated integrated circuit pin for providing external control during external master initiated DRAM accesses is removed by the implementation of a circuit and technique for multiplexing row and column addresses of the DRAM internally within the data processor.
摘要翻译： 外部总线主机（205）使用数据处理器（3）内部的存储器控制器（804）访问DRAM（207），而不使用外部多路复用器或任何其它外部电路。 通过实现用于在数据处理器内部复用DRAM的行和列地址的电路和技术来消除对在外部主发起的DRAM访问期间提供外部控制的外部多路复用器甚至专用集成电路引脚的需求。
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3.发明授权Method and apparatus for accessing a chip-selectable device in a data processing system 失效用于在数据处理系统中访问芯片可选设备的方法和装置
公开(公告)号：US5740382A
公开(公告)日：1998-04-14
申请号：US623482
申请日：1996-03-28
CPC分类号： G06F13/1694
摘要： A user may program a data processor (3) such that external master chip select accesses can be either the same or different length of time than an internal master access through the use of a control register (810). Additionally, the user can turn off the internal transfer acknowledge logic and add external transfer acknowledge logic while still using the internal chip select and write enable generation logic (8) of the data processor. This feature is user programmable on a chip select basis and provides a flexible solution which allows the user to compensate for different external master accesses without requiring external chip select and write enable logic. Therefore, overhead is conserved and efficiency is increased.
摘要翻译： 用户可以对数据处理器（3）进行编程，使得通过使用控制寄存器（810），外部主芯片选择访问可以与内部主机访问相同或不同的时间长度。 此外，用户可以在仍然使用数据处理器的内部芯片选择和写入使能生成逻辑（8）的同时关闭内部传输确认逻辑并添加外部传输确认逻辑。 该功能是用户可编程的芯片选择基础，并提供灵活的解决方案，允许用户补偿不同的外部主访问，而不需要外部芯片选择和写使能逻辑。 因此，节省开销，提高效率。
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公开(公告)号：US20140348181A1
公开(公告)日：2014-11-27
申请号：US13899731
申请日：2013-05-22
IPC分类号： H04J3/06
CPC分类号： H04J3/0667
摘要： A data processing node includes a local clock, a slave port and a time synchronization module. The slave port enables the data processing node to be connected through a node interconnect structure to a parent node that is operating in a time synchronized manner with a fabric time of the node interconnect structure. The time synchronization module is coupled to the local clock and the slave port. The time synchronization module is configured for collecting parent-centric time synchronization information and for using a local time provided by the local clock and the parent-centric time synchronization information for allowing one or more time-based functionality of the data processing node to be implemented in accordance with the fabric time.
摘要翻译： 数据处理节点包括本地时钟，从端口和时间同步模块。 从端口使得数据处理节点能够通过节点互连结构连接到以节点互连结构的结构时间的时间同步方式操作的父节点。 时间同步模块耦合到本地时钟和从端口。 时间同步模块被配置为收集以父为中心的时间同步信息，并且用于使用由本地时钟提供的本地时间和以父为中心的时间同步信息，以允许实现数据处理节点的一个或多个基于时间的功能 按照布料时间。
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公开(公告)号：US06981122B2
公开(公告)日：2005-12-27
申请号：US10255399
申请日：2002-09-26
申请人： Thomas A. Volpe , Michael S. Allen , Aaron Bauch
发明人： Thomas A. Volpe , Michael S. Allen , Aaron Bauch
CPC分类号： G06F12/0653
摘要： A memory system and a method for operating a memory system are provided. The memory system includes a set of memory banks, logic for calculating a first address in each memory bank from the set of memory banks and a controller receiving a transfer address from a computing device. The controller includes logic for selecting a memory bank from the set of memory banks based on the transfer address and the first addresses of the memory banks, and for mapping the transfer address to a target address in the selected memory bank based on a first address in the selected memory bank. As a result, the set of memory banks has a contiguous memory space.
摘要翻译： 提供了一种用于操作存储器系统的存储器系统和方法。 存储器系统包括一组存储器组，用于从存储器组集合计算每个存储器组中的第一地址的逻辑，以及从计算设备接收传输地址的控制器。 所述控制器包括用于基于所述传输地址和所述存储体的所述第一地址从所述存储体组中选择存储体的逻辑，以及用于基于所述存储体中的第一地址将所述传送地址映射到所述选择的存储体中的目标地址 所选择的存储体。 结果，存储器组的集合具有连续的存储器空间。
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公开(公告)号：US06895475B2
公开(公告)日：2005-05-17
申请号：US10261263
申请日：2002-09-30
申请人： Thomas A. Volpe , Michael S. Allen
发明人： Thomas A. Volpe , Michael S. Allen
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6022
摘要： Methods and apparatus are provided for supplying data to a processor in a digital processing system. The method includes holding data required by the processor in a cache memory, supplying data from the cache memory to the processor in response to processor requests, performing a cache line fill operation in response to a chache miss, supplying data from a prefetch buffer to the cache memory in response to the cache line fill operation, and speculatively loading data from a lower level memory to the prefetch buffer in response to the cache line fill operation.
摘要翻译： 提供了用于向数字处理系统中的处理器提供数据的方法和装置。 该方法包括将处理器所需的数据保存在高速缓冲存储器中，以响应于处理器请求将数据从高速缓冲存储器提供给处理器，响应于错误错误执行高速缓存行填充操作，将数据从预取缓冲器提供给 响应于高速缓存线填充操作的高速缓冲存储器，以及响应于高速缓存线填充操作，将低级存储器的数据推测加载到预取缓冲器。
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公开(公告)号：US20130107716A1
公开(公告)日：2013-05-02
申请号：US13659752
申请日：2012-10-24
申请人： Thomas A. Volpe , Mark Davis , David Borland , Ken Goss
发明人： Thomas A. Volpe , Mark Davis , David Borland , Ken Goss
IPC分类号： H04L12/24
CPC分类号： H04L41/0816 , H04L41/083 , H04L41/0833 , H04L41/0896 , H04L43/0888 , H04L47/25 , H04L49/10 , H04L49/30 , H04L49/351 , H04L49/40
摘要： A system and method for packet switching functionality focused on network aggregation that reduces size and power requirements of typical systems are provided in which the system and method also increases bandwidth and reduces latency from typical deployed systems.
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