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公开(公告)号：US07759987B2
公开(公告)日：2010-07-20
申请号：US12048895
申请日：2008-03-14
IPC分类号： H03B1/00
CPC分类号： H03K3/35613
摘要： A semiconductor integrated circuit includes a high-side transistor, a low-side transistor, a level shift circuit for driving the high-side transistor, and a pre-driver circuit for driving the low-side transistor. A connection point of the high-side transistor and the low-side transistor serves as an output terminal. The level shift circuit has first and second N-type MOS transistors whose gates are driven by the pre-driver circuit. The semiconductor integrated circuit further includes a diode whose anode is connected to the drain of the first or second N-type MOS transistor to which the gate of the high-side transistor is not connected, and whose cathode is connected to the output terminal.
摘要翻译： 半导体集成电路包括高侧晶体管，低侧晶体管，用于驱动高侧晶体管的电平移位电路和用于驱动低侧晶体管的预驱动电路。 高侧晶体管和低侧晶体管的连接点用作输出端子。 电平移位电路具有第一和第二N型MOS晶体管，其栅极由预驱动器电路驱动。 半导体集成电路还包括其阳极连接到第一或第二N型MOS晶体管的漏极的二极管，高侧晶体管的栅极未连接到该漏极，并且其阴极连接到输出端子。
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公开(公告)号：US20090045480A1
公开(公告)日：2009-02-19
申请号：US12094499
申请日：2006-11-07
IPC分类号： H01L27/02
CPC分类号： H01L27/0207 , H01L27/12
摘要： A semiconductor integrated circuit includes a plurality of circuit cells on a semiconductor chip. The plurality of circuit cells are formed along a first chip side of the semiconductor chip. Each of the plurality of circuit cells has a pad. The semiconductor integrated circuit further includes a high voltage potential interconnect formed over the plurality of circuit cells. The high voltage potential interconnect has a width expanding in a length direction from a center portion to end portions of the high voltage potential interconnect.
摘要翻译： 半导体集成电路包括半导体芯片上的多个电路单元。 多个电路单元沿半导体芯片的第一芯片侧形成。 多个电路单元中的每一个具有衬垫。 半导体集成电路还包括形成在多个电路单元上的高压电位互连。 高压电位互连具有从高压电位互连的中心部分到端部的长度方向上的宽度。
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公开(公告)号：US20080246529A1
公开(公告)日：2008-10-09
申请号：US12048895
申请日：2008-03-14
IPC分类号： H03L5/00 , H03K19/094
CPC分类号： H03K3/35613
摘要： A semiconductor integrated circuit includes a high-side transistor, a low-side transistor, a level shift circuit for driving the high-side transistor, and a pre-driver circuit for driving the low-side transistor. A connection point of the high-side transistor and the low-side transistor serves as an output terminal. The level shift circuit has first and second N-type MOS transistors whose gates are driven by the pre-driver circuit. The semiconductor integrated circuit further includes a diode whose anode is connected to the drain of the first or second N-type MOS transistor to which the gate of the high-side transistor is not connected, and whose cathode is connected to the output terminal.
摘要翻译： 半导体集成电路包括高侧晶体管，低侧晶体管，用于驱动高侧晶体管的电平移位电路和用于驱动低侧晶体管的预驱动电路。 高侧晶体管和低侧晶体管的连接点用作输出端子。 电平移位电路具有第一和第二N型MOS晶体管，其栅极由预驱动器电路驱动。 半导体集成电路还包括其阳极连接到第一或第二N型MOS晶体管的漏极的二极管，高侧晶体管的栅极未连接到该漏极，并且其阴极连接到输出端子。
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公开(公告)号：US07989964B2
公开(公告)日：2011-08-02
申请号：US12094494
申请日：2006-09-29
CPC分类号： H01L27/12 , G09G3/296 , H01L24/06 , H01L24/49 , H01L27/0207 , H01L27/11898 , H01L2224/05554 , H01L2224/06179 , H01L2224/49179 , H01L2924/00014 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： On a semiconductor chip in a semiconductor integrated circuit, a plurality of circuit cells each of which has a pad are formed along a first chip side of the semiconductor chip. Among the plurality of circuit cells, one or more circuit cells at least in the vicinity of an end portion on the first chip side are arranged having a steplike shift in a direction apart from the first chip side with decreasing distance from the center portion to the end portion on the first chip side.
摘要翻译： 在半导体集成电路中的半导体芯片上，沿着半导体芯片的第一芯片侧形成有具有焊盘的多个电路单元。 在多个电路单元中，至少在第一芯片侧的端部附近的一个或多个电路单元被布置成沿着与第一芯片侧分开的方向具有阶梯状移位，其中心部分到中间部分的距离减小 第一芯片侧的端部。
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公开(公告)号：US07323923B2
公开(公告)日：2008-01-29
申请号：US11211638
申请日：2005-08-26
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , G09G3/296 , G09G2330/04 , H03K3/012 , H03K19/0013
摘要： A driver circuit is provided for preventing generation of a pass-through current in a CMOS output unit even if a power supply voltage VDD supplied from a low voltage power supply drops below a recommended operating power supply voltage. The driver circuit includes a level shift unit having PMOS transistors and NMOS transistors, and a CMOS output unit having a PMOS transistor and an NMOS transistor. The source, drain and gate of one PMOS transistor are respectively connected to a high voltage power supply, a first contact and a second contact. The source, drain and gate of a second PMOS transistor are respectively connected to a high voltage power supply, the second contact and the first contact. The source of one NMOS transistor is grounded, the drain thereof is connected to the first contact, and the gate thereof receives a low voltage signal. The source of a second NMOS transistor is grounded, the drain thereof is connected to the second contact, and the gate thereof receives a low voltage signal. In this driver circuit, the driving current of the one PMOS transistor is higher than the driving current of the one NMOS transistor.
摘要翻译： 即使从低电压电源提供的电源电压VDD低于推荐的工作电源电压，也提供用于防止在CMOS输出单元中产生通过电流的驱动电路。 驱动器电路包括具有PMOS晶体管和NMOS晶体管的电平移位单元和具有PMOS晶体管和NMOS晶体管的CMOS输出单元。 一个PMOS晶体管的源极，漏极和栅极分别连接到高压电源，第一触点和第二触点。 第二PMOS晶体管的源极，漏极和栅极分别连接到高压电源，第二触点和第一触点。 一个NMOS晶体管的源极接地，其漏极连接到第一触点，其栅极接收低电压信号。 第二NMOS晶体管的源极接地，其漏极连接到第二触点，并且其栅极接收低电压信号。 在该驱动电路中，一个PMOS晶体管的驱动电流高于一个NMOS晶体管的驱动电流。
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公开(公告)号：US20070273412A1
公开(公告)日：2007-11-29
申请号：US11802635
申请日：2007-05-24
IPC分类号： H03B1/00
CPC分类号： G09G3/296 , G09G3/293 , G09G2310/0275 , G09G2330/06
摘要： A drive voltage supply circuit has a first wire line, a second wire line, a first drive circuit, a plurality of second drive circuits, a control circuit for driving the first drive circuit and the plurality of second drive circuits, and an impedance element connected between the first wire line and each of output terminals.
摘要翻译： 驱动电压供给电路具有第一有线线路，第二线路线路，第一驱动电路，多个第二驱动电路，用于驱动第一驱动电路和多个第二驱动电路的控制电路，以及连接有阻抗元件的阻抗元件 在第一线路和每个输出端子之间。
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公开(公告)号：US07969429B2
公开(公告)日：2011-06-28
申请号：US11941240
申请日：2007-11-16
申请人： Masahiko Sasada , Hiroki Matsunaga , Masashi Inao , Hiroshi Ando , Jinsaku Kaneda , Eisaku Maeda , Akihiro Maejima
发明人： Masahiko Sasada , Hiroki Matsunaga , Masashi Inao , Hiroshi Ando , Jinsaku Kaneda , Eisaku Maeda , Akihiro Maejima
IPC分类号： H01L29/739 , H01L31/00 , H03F3/16 , G09G3/28 , G09G5/00 , G06F3/038 , H01L27/10 , H01L29/73 , H03F3/04 , G09G3/20
CPC分类号： G09G3/296 , G09G3/282 , G09G3/294 , G09G2300/0408 , G09G2310/0289 , G09G2330/04
摘要： The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.
摘要翻译： 双极晶体管电路的集电极，发射极和基极分别连接到高侧电源端子，电平移位晶体管的漏极和浮动电源端子。 当高边输出晶体管导通时，浮动电源端子处于高电位电源端子的电位。 高侧电源端子通过恒定电压处于高于浮动电源端子的电位的电位。 开启电平移位晶体管时，其漏极电位降低到浮动电源端子的电位以下; 基极电流流过双极晶体管电路，电平移位晶体管的漏极电压钳位在浮动电源端子的电位附近; 双极晶体管电路导通，其集电极电流提供电平移位晶体管的漏极电流。
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8.发明授权Semiconductor integrated circuit device, PDP driver, and plasma display panel 有权半导体集成电路器件，PDP驱动器和等离子体显示面板公开(公告)号：US07855447B2
公开(公告)日：2010-12-21
申请号：US12067953
申请日：2007-03-22
IPC分类号： H01L23/52
CPC分类号： H01L24/06 , H01L23/50 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2224/05554 , H01L2224/05599 , H01L2224/0603 , H01L2224/48091 , H01L2224/4813 , H01L2224/48227 , H01L2224/4911 , H01L2224/49111 , H01L2224/49113 , H01L2224/4917 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/19043 , H01L2924/3011 , H01L2224/45099 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： In a semiconductor integrated circuit device of the present invention, temperature increase of a bonding wire can be suppressed even when conductive leads are short-circuited with each other, and reliability of the semiconductor integrated circuit device is improved. The conductive leads of a resin package for supplying a power supply section of a semiconductor integrated circuit chip with power from an external power supply are connected with bonding pads of the semiconductor integrated circuit chip by a plurality of bonding wires. Furthermore, the conductive leads connected to a GND for supplying the power supply section of the semiconductor integrated circuit chip with a grounding potential are connected with the bonding pads of the semiconductor integrated circuit chip by a plurality of bonding wires.
摘要翻译： 在本发明的半导体集成电路器件中，即使导电线彼此短路，也可以抑制接合线的温度升高，提高半导体集成电路器件的可靠性。 用于向外部电源供电的半导体集成电路芯片的电源部分的树脂封装的导电引线通过多根接合线与半导体集成电路芯片的接合焊盘连接。 此外，连接到用于向半导体集成电路芯片的电源部分提供接地电位的GND的导电引线通过多个接合线与半导体集成电路芯片的接合焊盘连接。
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公开(公告)号：US07469016B2
公开(公告)日：2008-12-23
申请号：US11290062
申请日：2005-11-30
IPC分类号： H04L25/34
CPC分类号： H03K3/00 , H03K17/00 , H03K17/693
摘要： A circuit for generating a ternary signal that receives a binary input-control signal and a binary reset signal and outputs a ternary signal. The circuit includes first to third transistors, each source terminal thereof is respectively connected to the three power supplies, and a sequential circuit that outputs control signals controlling the transistors. The sequential circuit outputs control signals that make the first and the third transistors be switched in a complementary manner in an initial state, and make the second and the third transistors be switched in a state that it is released from the initial state.
摘要翻译： 用于产生接收二进制输入控制信号和二进制复位信号并输出三进制信号的三态信号的电路。 电路包括第一至第三晶体管，其每个源极分别连接到三个电源，以及输出控制晶体管的控制信号的顺序电路。 顺序电路输出使得第一和第三晶体管在初始状态下以互补方式切换的控制信号，并且使第二和第三晶体管在从初始状态释放的状态下被切换。
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公开(公告)号：US07358968B2
公开(公告)日：2008-04-15
申请号：US10991243
申请日：2004-11-17
申请人： Masahiko Sasada , Hiroki Matsunaga , Masashi Inao , Hiroshi Ando , Jinsaku Kaneda , Eisaku Maeda , Akihiro Maejima
发明人： Masahiko Sasada , Hiroki Matsunaga , Masashi Inao , Hiroshi Ando , Jinsaku Kaneda , Eisaku Maeda , Akihiro Maejima
IPC分类号： H01L29/739 , H01L31/00 , H03F3/16 , G09G3/28 , G09G5/00 , G06F3/038 , H01L27/10 , H01L29/73 , H03F3/04 , G09G3/20
CPC分类号： G09G3/296 , G09G3/282 , G09G3/294 , G09G2300/0408 , G09G2310/0289 , G09G2330/04
摘要： The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.
摘要翻译： 双极晶体管电路的集电极，发射极和基极分别连接到高侧电源端子，电平移位晶体管的漏极和浮动电源端子。 当高边输出晶体管导通时，浮动电源端子处于高电位电源端子的电位。 高侧电源端子通过恒定电压处于高于浮动电源端子的电位的电位。 开启电平移位晶体管时，其漏极电位降低到浮动电源端子的电位以下; 基极电流流过双极晶体管电路，电平移位晶体管的漏极电压钳位在浮动电源端子的电位附近; 双极晶体管电路导通，其集电极电流提供电平移位晶体管的漏极电流。
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