公开(公告)号：US06678796B1

公开(公告)日：2004-01-13

申请号：US09679431

申请日：2000-10-03

申请人： Nicolai Kosche ,  Peter C. Damron ,  Joseph Chamdani ,  Partha Pal Tirumalai

发明人： Nicolai Kosche ,  Peter C. Damron ,  Joseph Chamdani ,  Partha Pal Tirumalai

IPC分类号： G06F1200

CPC分类号： G06F12/0862 ,  G06F8/4442 ,  G06F9/3802 ,  G06F2212/6028

摘要： A method and apparatus for scheduling instructions to provide adequate prefetch latency is disclosed during compilation of a program code in to a program. The prefetch scheduler component of the present invention selects a memory operation within the program code as a “martyr load” and removes the prefetch associated with the martyr load, if any. The prefetch scheduler takes advantage of the latency associated with the martyr load to schedule prefetches for memory operations which follow the martyr load. The prefetches are scheduled “behind” (i.e., prior to) the martyr load to allow the prefetches to complete before the associated memory operations are carried out. The prefetch schedule component continues this process throughout the program code to optimize prefetch scheduling and overall program operation.

摘要翻译： 在编程程序代码期间公开了一种用于调度指令以提供足够的预取延迟的方法和装置。 本发明的预取调度器部件选择程序代码内的存储器操作为“烈度加载”，并且删除与烈士负载相关联的预取（如果有的话）。 预取调度器利用与烈士负载相关联的延迟来调度针对烈士负载之后的存储器操作的预取。 预取被安排在“后面”（即在之前）烈士负载，以便在执行相关联的存储器操作之前完成预取。 预取计划组件在整个程序代码中继续此过程，以优化预取调度和整体程序操作。

公开(公告)号：US20070258380A1

公开(公告)日：2007-11-08

申请号：US11417087

申请日：2006-05-02

申请人： Joseph Chamdani ,  Michael Corwin ,  Joseph Pelissier ,  Michael Crater

发明人： Joseph Chamdani ,  Michael Corwin ,  Joseph Pelissier ,  Michael Crater

IPC分类号： H04J1/16 ,  H04L12/28

CPC分类号： H04L49/557 ,  H04L49/357 ,  H04L49/555

摘要： A method, system or switch device, the switch device being one of a ported and a non-ported switch device, either of which including a housing containing an ASIC providing a switching system within the switch device, the housing further including a plurality of extender ports communicating with the ASIC and being connectable to themselves either in loopback fashion or to one or more ported or non-ported switch devices, whereby the extender ports operate on a discrete protocol from standard switch ports. The ported switch device further includes a plurality of standard ports connectable to one or more external computer network devices. A switch device hereof is adapted to send and/or receive an identification communication, the identification communication adapted to be indicative of the health of a switch device or a connecting link in a switch system.

摘要翻译： 一种方法，系统或开关装置，所述开关装置是移动式和非端口式开关装置之一，所述开关装置中的任一种包括壳体，所述壳体包含在开关装置内提供开关系统的ASIC，所述壳体还包括多个延长器 端口与ASIC通信并且以环回方式连接到自身或者连接到一个或多个端口或非端口交换设备，由此扩展器端口以标准交换机端口的离散协议操作。 端口交换设备还包括可连接到一个或多个外部计算机网络设备的多个标准端口。 本发明的开关装置适于发送和/或接收识别通信，所述识别通信适于指示交换机设备或连接链路在交换系统中的健康状况。

公开(公告)号：US20070174597A1

公开(公告)日：2007-07-26

申请号：US11710112

申请日：2007-02-23

申请人： William Joy ,  Marc Tremblay ,  Gary Lauterbach ,  Joseph Chamdani

发明人： William Joy ,  Marc Tremblay ,  Gary Lauterbach ,  Joseph Chamdani

IPC分类号： G06F9/44

CPC分类号： G06F9/30141 ,  G06F9/30127 ,  G06F9/3804 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/4843 ,  G06F12/0842

摘要： A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.

公开(公告)号：US20070083625A1

公开(公告)日：2007-04-12

申请号：US11239954

申请日：2005-09-29

申请人： Joseph Chamdani ,  Gurumurthy Ramkumar ,  Bruce Younglove ,  Corey Hill

发明人： Joseph Chamdani ,  Gurumurthy Ramkumar ,  Bruce Younglove ,  Corey Hill

IPC分类号： G06F15/173

CPC分类号： H04L67/16 ,  H04Q3/0045 ,  H04Q3/66

摘要： Intelligent services are provided in a storage network using intelligent service modules that can be cabled to a switch external to the switch chassis and yet be managed as part of the switch's logical domain. Data and management communications between the intelligent service module and the core switch are provided through a “soft-backplane” implemented using in-band communications through cabling attached between the switch and the intelligent service module rather than through hardwired backplane within the chassis. Management communications from management software is directed to the switch, which handles the management functions relating to the intelligent service module or forwards the management requests to the intelligent service module for processing.

摘要翻译： 使用智能服务模块在存储网络中提供智能服务，智能服务模块可以连接到交换机机箱外部的交换机，并作为交换机逻辑域的一部分进行管理。 智能服务模块和核心交换机之间的数据和管理通信是通过连接在交换机和智能服务模块之间的布线，而不是通过机箱内的硬连线底板，通过带内通信实现的“软背板”来提供的。 来自管理软件的管理通信涉及交换机，其处理与智能服务模块相关的管理功能，或将管理请求转发到智能服务模块进行处理。

公开(公告)号：US06490658B1

公开(公告)日：2002-12-03

申请号：US08881013

申请日：1997-06-23

申请人： Sultan Ahmed ,  Joseph Chamdani

发明人： Sultan Ahmed ,  Joseph Chamdani

IPC分类号： G06F1206

CPC分类号： G06F12/1027 ,  G06F9/3455 ,  G06F9/383 ,  G06F9/3832 ,  G06F9/3861 ,  G06F12/0862 ,  G06F12/1054 ,  G06F2212/6022 ,  G06F2212/6024 ,  G06F2212/681

摘要： A memory cache method and apparatus with two memory execution pipelines, each having a translation lookaside buffer (TLB). Memory instructions are executed in the first pipeline (324) by searching a data cache (310) and a prefetch cache (320). A large data TLB (330) provides memory for storing address translations for the first pipeline (324) A second pipeline (328) executes memory instructions by accessing the prefetch cache (320). A second micro-TLB (340) is associated with the second pipeline (328). It is loaded in anticipation of data that will be referenced by the second pipeline (328). A history file (360) is also provided to retain information on previous instructions to aid in deciding when to prefetch data. Prefetch logic (370) determines when to prefetch data, and steering logic (380) routes certain instructions to the second pipeline (328) to increase system performance.

摘要翻译： 具有两个存储器执行管线的存储器高速缓存方法和装置，每个具有转换后备缓冲器（TLB）。 通过搜索数据高速缓存（310）和预取高速缓存（320），在第一流水线（324）中执行存储器指令。 大数据TLB（330）提供用于存储第一流水线（324）的地址转换的存储器。第二流水线（328）通过访问预取高速缓存（320）来执行存储器指令。 第二微型TLB（340）与第二管线（328）相关联。 预期将由第二管道（328）引用的数据加载。 还提供历史文件（360）以保留关于先前指令的信息，以帮助决定何时预取数据。 预取逻辑（370）确定何时预取数据，并且转向逻辑（380）将某些指令路由到第二管线（328）以增加系统性能。

公开(公告)号：US20070268825A1

公开(公告)日：2007-11-22

申请号：US11437186

申请日：2006-05-19

申请人： Michael Corwin ,  Joseph Chamdani ,  Stephen Trevitt

发明人： Michael Corwin ,  Joseph Chamdani ,  Stephen Trevitt

IPC分类号： H04L12/26

CPC分类号： H04L67/1017 ,  H04L47/50 ,  H04L47/60 ,  H04L67/1002 ,  H04L67/1008 ,  H04L67/1097 ,  H04L67/32

摘要： A scalable solution to managing fairness in a congested hierarchical switched system is disclosed. The solution comprises a means for managing fairness during congestion in a hierarchical switched system comprising a first level arbitration system and a second level arbitration system of a stage. The first level arbitration system comprises a plurality of arbitration segments that arbitrate between information flows received from at least one ingress point based upon weights associated with those information flows (or the ingress points). Each arbitration segment determines an aggregate weight from each active ingress point providing the information flows to the segment and forwards a selected information flow along with the aggregate weight (in-band or out-of-band) to the second level arbitration system. The second level arbitration system then arbitrates between information flows received from the arbitration segments of the first level arbitration system based upon the aggregate weights received along with those information flows. The second level arbitration system then forwards a selected information flow to an egress point of the stage. The stage may, for example, comprise a portion of a switch, a switch, or a switch network.

摘要翻译： 公开了一种用于管理拥塞分层交换系统中的公平性的可扩展解决方案。 解决方案包括一种用于管理分层交换系统中的拥塞期间的公平性的装置，包括阶段的第一级仲裁系统和第二级仲裁系统。 第一级仲裁系统包括多个仲裁段，其根据与这些信息流（或入口点）相关联的权重来仲裁从至少一个入口点接收的信息流之间。 每个仲裁段确定来自每个活动入口点的聚合权重，提供信息流到段，并将所选择的信息流与带宽或带外的总权重一起转发到第二级仲裁系统。 然后，第二级仲裁系统基于与这些信息流一起接收的总权重，在从第一级仲裁系统的仲裁段接收的信息流之间进行仲裁。 然后，第二级仲裁系统将所选择的信息流转发到舞台的出口点。 舞台可以例如包括开关的一部分，开关或开关网络。

公开(公告)号：US20070211640A1

公开(公告)日：2007-09-13

申请号：US11373711

申请日：2006-03-10

申请人： Subbarao Palacharla ,  Robert Matesevac ,  Litko Chan ,  Joseph Chamdani

发明人： Subbarao Palacharla ,  Robert Matesevac ,  Litko Chan ,  Joseph Chamdani

IPC分类号： H04L12/28 ,  H04J1/16 ,  H04L12/56 ,  H04L12/26

CPC分类号： H04L49/555 ,  H04L43/50 ,  H04L49/357

摘要： A method, system or switch device, the switch device having both switch and test capabilities. A method includes running in a test or switch mode or both; and, performing the testing operation or the switching operations, or both. Another method includes setting up the test functionality in the switch device, the test functionality including one or both of transmitting test data and receiving test data. Other steps may include initiating the transmission of test data; and checking the test data. A switch device may include an ASIC disposed within the switch device, the ASIC including one or both of an egress test block and an ingress test block; whereby the egress test block and the ingress test block are respectively adapted to transmit and receive a test packet; whereby the ASIC and one or both of the egress and ingress test blocks provide for alternatively operating in the conventional switch mode and in test mode.

摘要翻译： 一种方法，系统或开关装置，开关装置具有开关和测试能力。 一种方法包括以测试或切换模式运行或两者兼而有之; 并且执行测试操作或切换操作，或两者。 另一种方法包括设置交换设备中的测试功能，测试功能包括发送测试数据和接收测试数据中的一个或两个。 其他步骤可以包括启动测试数据的传输; 并检查测试数据。 开关设备可以包括设置在开关设备内的ASIC，ASIC包括出口测试块和入口测试块中的一个或两个; 由此出口测试块和入口测试块分别适于发送和接收测试分组; 由此ASIC和出口和入口测试块中的一个或两个提供在常规的开关模式和测试模式下的可替代地操作。

公开(公告)号：US20070147364A1

公开(公告)日：2007-06-28

申请号：US11317995

申请日：2005-12-22

申请人： Subbarao Palacharla ,  Yu Fang ,  Joseph Chamdani

发明人： Subbarao Palacharla ,  Yu Fang ,  Joseph Chamdani

IPC分类号： H04L12/56 ,  H04L12/28

CPC分类号： H04L45/00 ,  H04L45/583 ,  H04L49/45

摘要： A method, system or switch device, the switch device including an ASIC creating a switching system within the switch device, the ASIC including an ingress packet processor, an egress packet assembly device, a transmit control device and a routing device; whereby the ingress packet processor is disposed to receive a data packet, the routing device is adapted to route the data packet from the ingress packet processor to the egress packet assembly device and the transmit control device is disposed to control the routing of the routing device; the switch device further including an ingress port communicating with the ASIC and being connectable to one or more external computer network devices, the ingress port being a substantially standard switch port; an egress port communicating with the ASIC and being connectable to one or more external computer network devices, the egress port being a substantially standard switch port; and, an extender port, the extender port being connectable to another extender port in loopback fashion and being connectable to a corresponding extender port of a discrete switch device, whereby the extender port operates on a discrete protocol from the standard ports; whereby the ASIC is adapted to provide for alternatively transmitting a data packet locally to the egress port and remotely through the extender port.

摘要翻译： 一种方法，系统或交换设备，所述交换设备包括在所述交换设备内创建交换系统的ASIC，所述ASIC包括入口分组处理器，出口分组组装设备，发射控制设备和路由设备; 由此入口分组处理器被设置为接收数据分组，路由设备适于将数据分组从入口分组处理器路由到出口分组组装设备，并且发送控制设备被设置为控制路由设备的路由; 所述交换设备还包括与所述ASIC通信并可连接到一个或多个外部计算机网络设备的入口，所述入口是基本上标准的交换机端口; 与所述ASIC通信并可连接到一个或多个外部计算机网络设备的出口端口，所述出口是基本上标准的交换机端口; 扩展器端口可以环回方式连接到另一扩展器端口，并且可连接到离散交换设备的对应扩展器端口，由此扩展器端口从标准端口以离散协议操作; 由此ASIC适于提供将数据分组本地地发送到出口端口并且通过扩展器端口远程地发送。

公开(公告)号：US07185338B2

公开(公告)日：2007-02-27

申请号：US10271838

申请日：2002-10-15

申请人： Joseph Chamdani ,  Yuan Chou

发明人： Joseph Chamdani ,  Yuan Chou

IPC分类号： G06F9/46 ,  G06F9/44

CPC分类号： G06F9/3851 ,  G06F9/30134 ,  G06F9/3838 ,  G06F9/3842

摘要： A computer system includes a processor capable of executing a plurality of N threads of instructions, N being an integer greater than one, with a set of global registers visible to each of the plurality of threads and a plurality of busy bit memory elements used to signal whether or not a register is in use by a thread. The processor includes logic to stall a read from global register if the thread reading the global register is a speculative thread and the busy bits for prior threads are set. The processor might also include a speculative load address memory, into which speculative loads from speculative threads are entered and logic to compare addresses for stores from nonspeculative threads with addressees in the speculative load address memory and invalidate speculative threads corresponding to the speculative load addresses stored in the speculative load address memory. In an efficient implementation, aliasing load instructions can be distinct from nonaliasing load instructions, whereby addresses of aliasing load instructions are selectively stored in the speculative load address memory.

摘要翻译： 计算机系统包括能够执行多个N个指令线程的处理器，N是大于1的整数，其中一组全局寄存器对于多个线程中的每一个可见，以及用于发送信号的多个忙位存储器元件 线程是否使用寄存器。 如果读取全局寄存器的线程是推测线程，并且设置了先前线程的忙位，则处理器包括停止从全局寄存器读取的逻辑。 处理器还可以包括推测性加载地址存储器，其中输入来自推测性线程的推测性负载以及用于比较来自非特定线程的存储器的地址与推测性加载地址存储器中的收件人的逻辑，并使与存储在其中的推测负载地址相对应的推测线程无效 推测负载地址存储器。 在有效的实现中，混叠加载指令可以不同于非加密加载指令，由此将混叠加载指令的地址选择性地存储在推测加载地址存储器中。

公开(公告)号：US20070038679A1

公开(公告)日：2007-02-15

申请号：US11204975

申请日：2005-08-15

申请人： Gurumurthy Ramkumar ,  Larry Hofer ,  Sunil Ramesh ,  Joseph Chamdani ,  Raj Cherabuddi ,  Greg Majszak

发明人： Gurumurthy Ramkumar ,  Larry Hofer ,  Sunil Ramesh ,  Joseph Chamdani ,  Raj Cherabuddi ,  Greg Majszak

IPC分类号： G06F17/30

CPC分类号： H04L41/082 ,  H04L41/0823 ,  H04L67/1097

摘要： Differential configuration update commands can be communicated and applied quickly and efficiently to active zone sets and zone set libraries, without requiring propagation of entire zone sets through a fabric of a SAN. Furthermore, the commands can be applied quickly to support dynamic configuration updates. Ordered differential configuration update commands can be applied to ordered zone set data structures to minimize update instruction communication requirements and optimize configuration update operations. In addition, differential configuration update commands can be applied to active zone set data structures (e.g., in an active zone set or a zone set library) to optimize configuration update operations.

摘要翻译： 可以将差异配置更新命令快速有效地传达和应用于活动区域集和区域集库，而不需要通过SAN的结构传播整个区域集。 此外，可以快速应用这些命令来支持动态配置更新。 有序的差分配置更新命令可以应用于有序区域集数据结构，以最小化更新指令通信要求并优化配置更新操作。 此外，差分配置更新命令可以应用于活动区域集数据结构（例如，在活动区域​​集合或区域集库中）以优化配置更新操作。