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    PROCESS FOR FORMING AN EPITAXIAL LAYER, IN PARTICULAR ON THE SOURCE AND DRAIN REGIONS OF FULLY-DEPLETED TRANSISTORS
    1.
    发明申请
    PROCESS FOR FORMING AN EPITAXIAL LAYER, IN PARTICULAR ON THE SOURCE AND DRAIN REGIONS OF FULLY-DEPLETED TRANSISTORS 审中-公开
    形成外延层的方法，特别是完全放电的晶体管的源和漏区

    公开(公告)号：US20120252174A1

    公开(公告)日：2012-10-04

    申请号：US13434923

    申请日：2012-03-30

    申请人： Didier Dutartre ,  Nicolas Loubet ,  Yves Campidelli ,  Denis Pellissier-Tanon

    发明人： Didier Dutartre ,  Nicolas Loubet ,  Yves Campidelli ,  Denis Pellissier-Tanon

    IPC分类号： H01L21/336 ,  H01L21/20

    CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7848

    摘要： A layer of a semiconductor material is epitaxially grown on a single-crystal semiconductor structure and on a polycrystalline semiconductor structure. The epitaxial layer is then etched in order to preserve a non-zero thickness of said material on the single-crystal structure and a zero thickness on the polycrystalline structure. The process of growth and etch is repeated, with the same material or with a different material in each repetition, until a stack of epitaxial layers on said single-crystal structure has reached a desired thickness. The single crystal structure is preferably a source/drain region of a transistor, and the polycrystalline structure is preferably a gate of that transistor.

    摘要翻译： 在单晶半导体结构和多晶半导体结构上外延生长半导体材料层。 然后蚀刻外延层，以便在单晶结构上保留所述材料的非零厚度，并在多晶结构上保持零厚度。 在每个重复中，使用相同的材​​料或不同的材料重复生长和蚀刻的过程，直到所述单晶结构上的一叠外延层已经达到期望的厚度。 单晶结构优选为晶体管的源/漏区，多晶结构优选为该晶体管的栅极。

    Process for nitriding the gate oxide layer of a semiconductor device and device obtained
    7.
    发明授权
    Process for nitriding the gate oxide layer of a semiconductor device and device obtained 失效
    用于氮化半导体器件的栅极氧化物层的工艺和所获得的器件

    公开(公告)号：US06372581B1

    公开(公告)日：2002-04-16

    申请号：US09403356

    申请日：1999-10-18

    申请人： Daniel Bensahel ,  Yves Campidelli ,  François Martin ,  Caroline Hernandez

    发明人： Daniel Bensahel ,  Yves Campidelli ,  François Martin ,  Caroline Hernandez

    IPC分类号： H01L21336

    CPC分类号： H01L21/28202 ,  H01L21/28238 ,  H01L29/513 ,  H01L29/518

    摘要： A method of nitriding the gate oxide layer of a semiconductor device includes the chemical growth on a silicon substrate of a native silicon oxide layer ≦1 nm thick; treating said substrate coated with the native silicon oxide layer with gas NO at a temperature ≦700° C. and a pressure level ≦104 Pa to obtain a nitrided native silicon oxide layer; and the growth of the gate oxide layer. The method is applicable to PMOS devices. Further modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in view of this description. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the general manner of carrying out the invention. It is to be understood that the forms of the invention shown and described herein are to be taken as the presently preferred embodiments. Elements and materials may be substituted for those illustrated and described herein, parts and processes may be reversed, and certain features of the invention may be utilized independently, all as would be apparent to one skilled in the art after having the benefit of this description of the invention. Changes may be made in the elements described herein without departing from the spirit and scope of the invention as described in the following claims.

    摘要翻译： 氮化半导体器件的栅极氧化物层的方法包括在硅衬底上的化学生长，其厚度为1nm的天然氧化硅层; 在温度<= 700℃和压力水平<= 104Pa下用气体NO处理涂覆有天然氧化硅层的所述衬底，以获得氮化的天然氧化硅层; 以及栅氧化层的生长。 该方法适用于PMOS器件。鉴于本说明书，本发明的各个方面的进一步修改和替代实施例对于本领域技术人员将是显而易见的。 因此，该描述仅被解释为说明性的，并且是为了教导本领域技术人员进行本发明的一般方式的目的。 应当理解，本文示出和描述的本发明的形式将被视为当前优选的实施例。 元件和材料可以代替本文所示出和描述的那些，部件和工艺可以颠倒，并且本发明的某些特征可以独立地使用，这一切如本领域技术人员在获得本说明书的益处之后显而易见的 本发明。 在不脱离如所附权利要求所述的本发明的精神和范围的情况下，可以对本文所述的元件进行改变。

    Single-crystal layer on a dielectric layer
    8.
    发明授权
    Single-crystal layer on a dielectric layer 有权
    电介质层上的单晶层

    公开(公告)号：US07547914B2

    公开(公告)日：2009-06-16

    申请号：US11653760

    申请日：2007-01-16

    申请人： Olivier Kermarec ,  Yves Campidelli ,  Guillaume Pin

    发明人： Olivier Kermarec ,  Yves Campidelli ,  Guillaume Pin

    IPC分类号： H01L31/036

    CPC分类号： H01L21/7624 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02661

    摘要： The process relates to the production of a layer of a single-crystal first material on a second material. The second material has at least one aperture exposing a surface portion of a single-crystal third material. The process generally includes forming an at least partially crystalline first layer of said first material on said surface portion of the third material. Then, an amorphous or partially crystalline second layer of the first material is formed on the at least partially crystalline first layer of the first material and on one part of the second material that is around said aperture. Finally, the process includes recrystallization annealing of the first material. Thus, it is possible to produce, within one and the same wafer, either transistors on a germanium-on-insulator substrate with transistors on a silicon-on-insulator substrate, or transistors on a germanium-on-insulator substrate with transistors on a silicon substrate.

    摘要翻译： 该方法涉及在第二材料上生产单晶第一材料层。 第二材料具有暴露单晶第三材料的表面部分的至少一个孔。 该方法通常包括在第三材料的所述表面部分上形成所述第一材料的至少部分结晶的第一层。 然后，第一材料的无定形或部分结晶的第二层形成在第一材料的至少部分结晶的第一层上和在围绕所述孔的第二材料的一部分上。 最后，该方法包括第一材料的再结晶退火。 因此，可以在同一晶片内产生绝缘体上的衬底上的晶体管，其中绝缘体上硅衬底上的晶体管或绝缘体上锗衬底上的晶体管，其上具有晶体管 硅衬底。