公开(公告)号：US11768781B2

公开(公告)日：2023-09-26

申请号：US17827556

申请日：2022-05-27

申请人： Niranjan L. Cooray ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran ,  Satyeshwar Singh ,  Sameer Kp ,  Ankur N. Shah ,  Kun Tian

发明人： Niranjan L. Cooray ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran ,  Satyeshwar Singh ,  Sameer Kp ,  Ankur N. Shah ,  Kun Tian

IPC分类号： G06F9/455 ,  G06F9/50 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

CPC分类号： G06F13/16 ,  G06F12/0802 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F13/4068 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/60 ,  G06F2212/68

摘要： An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US20180307487A1

公开(公告)日：2018-10-25

申请号：US15493442

申请日：2017-04-21

申请人： Subramaniam M. Maiyuran ,  Guei-Yuan Lueh ,  Supratim Pal ,  Gang Chen ,  Ananda V. Kommaraju ,  Joy Chandra ,  Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Hong Bin Liao ,  Joydeep Ray ,  Abhishek R. Appu ,  Ankur N. Shah ,  Travis T. Schluessler ,  Jonathan Kennedy ,  Devan Burke

发明人： Subramaniam M. Maiyuran ,  Guei-Yuan Lueh ,  Supratim Pal ,  Gang Chen ,  Ananda V. Kommaraju ,  Joy Chandra ,  Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Hong Bin Liao ,  Joydeep Ray ,  Abhishek R. Appu ,  Ankur N. Shah ,  Travis T. Schluessler ,  Jonathan Kennedy ,  Devan Burke

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06T1/20

摘要： An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.

公开(公告)号：US20180285191A1

公开(公告)日：2018-10-04

申请号：US15477050

申请日：2017-04-01

申请人： Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Eric C. Samson ,  Joydeep Ray ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Ankur N. Shah ,  Altug Koker

发明人： Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Eric C. Samson ,  Joydeep Ray ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Ankur N. Shah ,  Altug Koker

IPC分类号： G06F11/07

摘要： Methods and apparatus relating to techniques for reference voltage control based on error detection are described. In an embodiment, modification to a reference voltage (to be supplied to one or more components of a processor) is based at least in part on error detection to be detected for a reference circuit. In another embodiment, modification is made to a power characteristic of a processor in response to a determination that the processor is to execute a safety critical application. The modification may include adjustment to an operating frequency and/or an operating voltage of the processor. Other embodiments are also disclosed and claimed.

公开(公告)号：US10719917B2

公开(公告)日：2020-07-21

申请号：US16243490

申请日：2019-01-09

申请人： Tomer Bar-On ,  Hugues Labbe ,  Adam T. Lake ,  Kai Xiao ,  Ankur N. Shah ,  Johannes Guenther ,  Abhishek R. Appu ,  Joydeep Ray ,  Deepak S. Vembar ,  ElMoustapha Ould-Ahmed-Vall

发明人： Tomer Bar-On ,  Hugues Labbe ,  Adam T. Lake ,  Kai Xiao ,  Ankur N. Shah ,  Johannes Guenther ,  Abhishek R. Appu ,  Joydeep Ray ,  Deepak S. Vembar ,  ElMoustapha Ould-Ahmed-Vall

IPC分类号： G06T5/00 ,  G06T1/20 ,  G06T15/00 ,  G06T15/50 ,  G06T9/00 ,  G06T11/40

摘要： Systems, apparatuses and methods may provide for technology that identifies, at an image post-processor, unresolved surface data and identifies, at the image post-processor, control data associated with the unresolved surface data. Additionally, the technology may resolve, at the image post-processor, the unresolved surface data and the control data into a final image.

公开(公告)号：US20190251666A1

公开(公告)日：2019-08-15

申请号：US16243490

申请日：2019-01-09

申请人： Tomer Bar-On ,  Hugues Labbe ,  Adam T. Lake ,  Kai Xiao ,  Ankur N. Shah ,  Johannes Guenther ,  Abhishek R. Appu ,  Joydeep Ray ,  Deepak S. Vembar ,  ElMoustapha Ould-Ahmed-Vall

发明人： Tomer Bar-On ,  Hugues Labbe ,  Adam T. Lake ,  Kai Xiao ,  Ankur N. Shah ,  Johannes Guenther ,  Abhishek R. Appu ,  Joydeep Ray ,  Deepak S. Vembar ,  ElMoustapha Ould-Ahmed-Vall

IPC分类号： G06T5/00 ,  G06T11/40 ,  G06T9/00 ,  G06T15/50 ,  G06T1/20 ,  G06T15/00

CPC分类号： G06T5/002 ,  G06T1/20 ,  G06T9/00 ,  G06T11/40 ,  G06T15/005 ,  G06T15/503 ,  G06T2200/12

摘要： Systems, apparatuses and methods may provide for technology that identifies, at an image post-processor, unresolved surface data and identifies, at the image post-processor, control data associated with the unresolved surface data. Additionally, the technology may resolve, at the image post-processor, the unresolved surface data and the control data into a final image.

公开(公告)号：US20150379667A1

公开(公告)日：2015-12-31

申请号：US14318893

申请日：2014-06-30

申请人： Nishanth Reddy Pendluru ,  Jeffrey S. Frizzell ,  Ankur N. Shah

发明人： Nishanth Reddy Pendluru ,  Jeffrey S. Frizzell ,  Ankur N. Shah

IPC分类号： G06T1/20

CPC分类号： G06T1/20 ,  G09G5/006 ,  G09G5/14 ,  G09G5/363 ,  G09G2340/02 ,  G09G2360/08 ,  G09G2360/121

摘要： Described herein are technologies related to performing of a preemption operation in graphics hardware. Particularly, the preemption operation includes tracking of unreported or dropped workload independent of workloads submitted to the graphics hardware.

摘要翻译： 这里描述了与在图形硬件中执行抢占操作有关的技术。 特别地，抢占操作包括跟踪提交给图形硬件的工作负载的未报告或丢弃的工作负载。

公开(公告)号：US20140049551A1

公开(公告)日：2014-02-20

申请号：US13588308

申请日：2012-08-17

申请人： Jayanth N. Rao ,  Ronald W. Silvas ,  Ankur N. Shah

发明人： Jayanth N. Rao ,  Ronald W. Silvas ,  Ankur N. Shah

IPC分类号： G06T11/60

CPC分类号： G06T1/60 ,  G06F12/0223 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/126 ,  G06F2212/302 ,  G06F2212/62 ,  G06F2212/656 ,  G06F2212/657 ,  G06T1/20 ,  G06T11/60 ,  Y02D10/13

摘要： A method and system for shared virtual memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a system memory. A CPU virtual address space may be created, and the surface may be mapped to the CPU virtual address space within a CPU page table. The method also includes creating a GPU virtual address space equivalent to the CPU virtual address space, mapping the surface to the GPU virtual address space within a GPU page table, and pinning the surface.

摘要翻译： 本文公开了一种用于计算设备的中央处理单元（CPU）和图形处理单元（GPU）之间的共享虚拟存储器的方法和系统。 该方法包括在系统存储器内分配表面。 可以创建CPU虚拟地址空间，并且可以将表面映射到CPU页表中的CPU虚拟地址空间。 该方法还包括创建等效于CPU虚拟地址空间的GPU虚拟地址空间，将表面映射到GPU页表中的GPU虚拟地址空间，并固定表面。

公开(公告)号：US09378572B2

公开(公告)日：2016-06-28

申请号：US13588308

申请日：2012-08-17

申请人： Jayanth N. Rao ,  Ronald W. Silvas ,  Ankur N. Shah

发明人： Jayanth N. Rao ,  Ronald W. Silvas ,  Ankur N. Shah

IPC分类号： G06F12/02 ,  G06T11/60 ,  G06T1/60 ,  G06F12/10 ,  G06F12/12

CPC分类号： G06T1/60 ,  G06F12/0223 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/126 ,  G06F2212/302 ,  G06F2212/62 ,  G06F2212/656 ,  G06F2212/657 ,  G06T1/20 ,  G06T11/60 ,  Y02D10/13

摘要： A method and system for shared virtual memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a system memory. A CPU virtual address space may be created, and the surface may be mapped to the CPU virtual address space within a CPU page table. The method also includes creating a GPU virtual address space equivalent to the CPU virtual address space, mapping the surface to the GPU virtual address space within a GPU page table, and pinning the surface.

摘要翻译： 本文公开了一种用于计算设备的中央处理单元（CPU）和图形处理单元（GPU）之间的共享虚拟存储器的方法和系统。 该方法包括在系统存储器内分配表面。 可以创建CPU虚拟地址空间，并且可以将表面映射到CPU页表中的CPU虚拟地址空间。 该方法还包括创建等效于CPU虚拟地址空间的GPU虚拟地址空间，将表面映射到GPU页表中的GPU虚拟地址空间，并固定表面。

公开(公告)号：US20150379662A1

公开(公告)日：2015-12-31

申请号：US14315626

申请日：2014-06-26

申请人： Murali Ramadoss ,  Nishanth R. Pendluru ,  Jeffrey S. Frizzell ,  Ankur N. Shah

发明人： Murali Ramadoss ,  Nishanth R. Pendluru ,  Jeffrey S. Frizzell ,  Ankur N. Shah

IPC分类号： G06T1/20

CPC分类号： G06T1/20 ,  G06F9/5044 ,  G06F2209/509 ,  Y02D10/22

摘要： Methods and systems may provide for receiving, at a controller, a notification of a workload submission by an application lacking system level privileges. Additionally, the controller may be used to schedule a transfer of the workload submission to a graphics hardware component for execution, wherein the controller has system level privileges. In one example, the transfer bypasses an operating system and a kernel mode driver associated with the graphics hardware component.

摘要翻译： 方法和系统可以规定在控制器处由缺少系统级特权的应用程序接收工作负载提交的通知。 此外，控制器可以用于调度将工作负载提交传送到图形硬件组件以供执行，其中控制器具有系统级特权。 在一个示例中，转移绕过与图形硬件组件相关联的操作系统和内核模式驱动器。