公开(公告)号：US5578508A

公开(公告)日：1996-11-26

申请号：US426233

申请日：1995-04-21

申请人： Yoshiro Baba ,  Satoshi Yanagiya ,  Noboru Matsuda ,  Akihiko Osawa ,  Masanobu Tsuchitani

发明人： Yoshiro Baba ,  Satoshi Yanagiya ,  Noboru Matsuda ,  Akihiko Osawa ,  Masanobu Tsuchitani

IPC分类号： H01L21/302 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L21/336 ,  H01L29/78 ,  H01L21/304 ,  H01L21/76

CPC分类号： H01L29/7813 ,  H01L29/66734 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/7838

摘要： A channel region and a source region are formed on a surface of a substrate by double diffusion. A trench is formed so as to penetrate a part of the channel region and a part of the source region and reach the substrate. After an insulating film is formed on an inner wall of the trench, a polysilicon layer is buried up to an intermediate portion of the trench. In this state, channel ions are implanted in a side surface region of the trench, thereby depleting a channel region. Thereafter, a polysilicon layer for leading out a gate is buried in the trench.

摘要翻译： 通过双扩散在衬底的表面上形成沟道区域和源极区域。 形成沟槽，以便穿透沟道区域的一部分和源区域的一部分并到达衬底。 在沟槽的内壁上形成绝缘膜之后，将多晶硅层埋入沟槽的中间部分。 在这种状态下，沟道离子注入沟槽的侧表面区域，从而耗尽沟道区域。 此后，用于引出栅极的多晶硅层被埋在沟槽中。

公开(公告)号：US5770514A

公开(公告)日：1998-06-23

申请号：US787573

申请日：1997-01-22

申请人： Noboru Matsuda ,  Yoshiro Baba ,  Satoshi Yanagiya ,  Masanobu Tsuchitani

发明人： Noboru Matsuda ,  Yoshiro Baba ,  Satoshi Yanagiya ,  Masanobu Tsuchitani

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/423 ,  H01L29/739 ,  H01L29/772 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/7397 ,  H01L29/7813 ,  H01L29/4232 ,  H01L29/4238

摘要： In a vertical field effect transistor having a trench gate and a method of manufacturing the same according to the present invention, p-type base and n.sup.+ -type source diffusion layers are formed in this order in a surface region of an n.sup.31 -type epitaxial layer on an n.sup.+ -type semiconductor substrate. A trench is then provided to such a depth as to penetrate the diffusion layers. A dope polysilicon layer is deposited and buried into the trench with a gate insulation film interposed between them. The polysilicon layer is etched to have the same level as that of the entrance of the trench, and a dope polysilicon layer 18 is selectively grown thereon, thereby forming a trench gate in which an upper corner portion of the trench is not covered with a gate electrode. Consequently, the concentration of electric fields at the corner portion can be mitigated thereby to increase an absolute withstand voltage of the gate and the variations in threshold voltage can be suppressed in a BT test.

摘要翻译： 在根据本发明的具有沟槽栅的垂直场效应晶体管及其制造方法中，在n31型外延层的表面区域中依次形成p型基极和n +型源极扩散层 在n +型半导体衬底上。 然后将沟槽提供到穿透扩散层的深度。 将掺杂多晶硅层沉积并埋入沟槽中，并在其间插入栅极绝缘膜。 蚀刻多晶硅层以与沟槽的入口具有相同的电平，并且在其上选择性地生长掺杂多晶硅层18，从而形成沟槽栅极，其中沟槽的上角部分未被栅极覆盖 电极。 因此，可以减轻角部处的电场的集中，从而提高栅极的绝对耐受电压，并且可以在BT测试中抑制阈值电压的变化。

公开(公告)号：US6060747A

公开(公告)日：2000-05-09

申请号：US159122

申请日：1998-09-23

申请人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba ,  Noboru Matsuda ,  Masanobu Tsuchitani

发明人： Hideki Okumura ,  Akihiko Osawa ,  Yoshiro Baba ,  Noboru Matsuda ,  Masanobu Tsuchitani

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/739

CPC分类号： H01L29/0696

摘要： A semiconductor device is characterized in that source electrode contact regions, each of which is formed of a first conductivity type source layer and a second conductivity type base layer in a surface of a semiconductor surface, are formed at respective intersectional points of a diagonally-arranged lattice, and in that a trench having a gate electrode buried therein is formed so as to snake through the contact regions alternately. By virtue of the structure, the trench arrangement and source/base simultaneous contact quality are improved, to thereby increase a trench density (channel density) per unit area.

摘要翻译： 半导体器件的特征在于，在对角线布置的各个交点处形成源极电极接触区域，每个源极电极接触区域由半导体表面的第一导电型源极层和第二导电型基极层形成， 并且具有埋入其中的具有栅电极的沟槽形成为交替地穿过接触区域。 通过该结构，提高了沟槽布置和源极/基极同时接触质量，从而增加了每单位面积的沟槽密度（沟道密度）。

公开(公告)号：US5610422A

公开(公告)日：1997-03-11

申请号：US510654

申请日：1995-08-03

申请人： Satoshi Yanagiya ,  Noboru Matsuda ,  Yoshiro Baba

发明人： Satoshi Yanagiya ,  Noboru Matsuda ,  Yoshiro Baba

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L29/7827 ,  H01L29/42368 ,  H01L29/4238

摘要： In a vertical power MOSFET having a U-shaped trench gate and a method of manufacturing the same, a P-type base layer and an N.sup.+ -type emitter layer are formed on the surface of an N-type semiconductor substrate. A plurality of trenches are formed to such a depth as to reach the semiconductor substrate. After that, an oxide film and a nitride film are formed in this order on the surface of the resultant element and on the inner surfaces of the trenches. In this case, the oxide film and nitride film are each formed to have a thickness corresponding to the operating characteristics of the element at the stage of design. The nitride film of a gate wiring region is selectively removed to form an oxide film on the surface of the element. Consequently, a thick gate insulation film of the oxide films can be formed between the corner portions of the N.sup.+ -type emitter layer and a gate electrode wiring layer of the gate wiring region which is to be formed afterward, and the gate-to-source breakdown voltage can be enhanced.

摘要翻译： 在具有U形沟槽栅极的垂直功率MOSFET及其制造方法中，在N型半导体衬底的表面上形成P型基极层和N +型发射极层。 多个沟槽形成为达到半导体衬底的深度。 此后，在所得元件的表面和沟槽的内表面上依次形成氧化物膜和氮化物膜。 在这种情况下，氧化膜和氮化物膜各自形成为具有与设计阶段的元件的工作特性对应的厚度。 选择性地去除栅极布线区域的氮化物膜以在元件的表面上形成氧化物膜。 因此，可以在N +型发射极层的角部与之后形成的栅极配线区域的栅电极配线层之间形成氧化物膜的厚栅极绝缘膜，栅极至源极 可以提高击穿电压。

公开(公告)号：US5726088A

公开(公告)日：1998-03-10

申请号：US746846

申请日：1996-11-15

申请人： Satoshi Yanagiya ,  Noboru Matsuda ,  Yoshiro Baba

发明人： Satoshi Yanagiya ,  Noboru Matsuda ,  Yoshiro Baba

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7827 ,  H01L29/42368 ,  H01L29/4238

摘要： In a vertical power MOSFET having a U-shaped trench gate and a method of manufacturing the same, a P-type base layer and an N.sup.+ -type emitter layer are formed on the surface of an N-type semiconductor substrate. A plurality of trenches are formed to such a depth as to reach the semiconductor substrate. After that, an oxide film and a nitride film are formed in this order on the surface of the resultant element and on the inner surfaces of the trenches. In this case, the oxide film and nitride film are each formed to have a thickness corresponding to the operating characteristics of the element at the stage of design. The nitride film of a gate wiring region is selectively removed to form an oxide film on the surface of the element. Consequently, a thick gate insulation film of the oxide films can be formed between the corner portions of the N.sup.+ -type emitter layer and a gate electrode wiring layer of the gate wiring region which is to be formed afterward, and the gate-to-source breakdown voltage can be enhanced.

摘要翻译： 在具有U形沟槽栅极的垂直功率MOSFET及其制造方法中，在N型半导体衬底的表面上形成P型基极层和N +型发射极层。 多个沟槽形成为达到半导体衬底的深度。 此后，在所得元件的表面和沟槽的内表面上依次形成氧化物膜和氮化物膜。 在这种情况下，氧化膜和氮化物膜各自形成为具有与设计阶段的元件的工作特性对应的厚度。 选择性地去除栅极布线区域的氮化物膜以在元件的表面上形成氧化物膜。 因此，可以在N +型发射极层的角部与之后形成的栅极配线区域的栅电极配线层之间形成氧化物膜的厚栅极绝缘膜，栅极至源极 可以提高击穿电压。

公开(公告)号：US20060091453A1

公开(公告)日：2006-05-04

申请号：US11208619

申请日：2005-08-23

申请人： Noboru Matsuda ,  Koichi Takahashi ,  Keiko Kawamura ,  Masanobu Tsuchitani

发明人： Noboru Matsuda ,  Koichi Takahashi ,  Keiko Kawamura ,  Masanobu Tsuchitani

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/515 ,  H01L29/66734

摘要： A trench MIS device includes a drain region, a base region disposed on the drain region, the base region having a channel face, a source region disposed on the base region, the source region having a source end face, the source end face being continuous with the channel face, a gate insulator disposed along the channel face and the source end face, a gate electrode disposed opposite to the channel face through the gate insulator, and a cavity portion provided in the drain region, the cavity portion being opposite to the gate electrode.

摘要翻译： 沟槽MIS器件包括漏极区域，设置在漏极区域上的基极区域，具有沟道面的基极区域，设置在基极区域上的源极区域，源极区域具有源极端面，源极端面连续 所述沟道面具有沿沟道面和源极端面配置的栅极绝缘体，通过栅极绝缘体与沟道面相对设置的栅极电极和设置在漏极区域中的空腔部分，空腔部分与漏极区域相对 栅电极。

公开(公告)号：US5917228A

公开(公告)日：1999-06-29

申请号：US800028

申请日：1997-02-13

申请人： Noboru Matsuda ,  Yoshiro Baba

发明人： Noboru Matsuda ,  Yoshiro Baba

IPC分类号： H01L21/329 ,  H01L29/47 ,  H01L29/861 ,  H01L29/872 ,  H01L31/107

CPC分类号： H01L29/66143 ,  H01L29/872

摘要： The present invention relates to a schottky-barrier diode capable of decreasing a leakage current due to damage generated on inner walls of trenches, and securing a large operation region for itself. In the device, an N.sup.- -type epitaxial layer is formed on a N.sup.+ -type silicon substrate. In a predetermined region in the epitaxial layer, a P.sup.+ -type base diffusion layer having high impurity concentration is formed. Trenches are formed through from the surface of the base diffusion layer to the epitaxial layer. In each of the trenches, an N.sup.- -type selective epitaxial growth region is formed. A schottky metal is formed on a surface comprising the surfaces of the base diffusion layer, which includes the selective epitaxial growth regions, and the epitaxial layer. Surface regions as the surfaces of the selective epitaxial growth regions filling the trenches function as diode operation regions.

摘要翻译： 本发明涉及一种肖特基势垒二极管，其能够减少由沟槽内壁产生的损伤引起的漏电流，并且可以确保其自身的大的操作区域。 在器件中，在N +型硅衬底上形成N型外延层。 在外延层的预定区域中，形成杂质浓度高的P +型基极扩散层。 沟槽形成为从基底扩散层的表面到外延层。 在每个沟槽中，形成N型选择性外延生长区。 在包括选择性外延生长区的基底扩散层的表面和外延层的表面上形成肖特基金属。 作为填充沟槽的选择性外延生长区域的表面的表面区域用作二极管操作区域。

公开(公告)号：US07049657B2

公开(公告)日：2006-05-23

申请号：US10714868

申请日：2003-11-18

申请人： Noboru Matsuda

发明人： Noboru Matsuda

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/62 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/42368

摘要： A semiconductor device comprises: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a trench; a thick gate insulating film; a thin gate insulating film; a gate electrode; and a semiconductor region of a second conductivity type. The second semiconductor layer is provided on the first semiconductor layer. The trench penetrates the second semiconductor layer and intrudes into the first semiconductor layer. The thick gate insulating film is provided on a inner wall of the trench below an upper surface of the first semiconductor layer. The thin gate insulating film is provided on the inner wall of the trench at a part upper than the thick gate insulating film. The gate electrode fills the trench. The semiconductor region of a second conductivity type is selectively formed to adjoin the trench and to project from a bottom surface of the second semiconductor layer into the first semiconductor layer.

摘要翻译： 一种半导体器件包括：第一导电类型的第一半导体层; 第二导电类型的第二半导体层; 沟渠 厚栅绝缘膜; 薄栅绝缘膜; 栅电极; 和第二导电类型的半导体区域。 第二半导体层设置在第一半导体层上。 沟槽穿透第二半导体层并侵入第一半导体层。 厚栅极绝缘膜设置在第一半导体层的上表面下方的沟槽的内壁上。 薄栅极绝缘膜设置在沟槽的内壁上方的厚栅极绝缘膜的上方。 栅电极填充沟槽。 选择性地形成第二导电类型的半导体区域以邻接沟槽并从第二半导体层的底表面突出到第一半导体层。

公开(公告)号：US20060086972A1

公开(公告)日：2006-04-27

申请号：US11062838

申请日：2005-02-23

申请人： Hironobu Shibata ,  Noboru Matsuda

发明人： Hironobu Shibata ,  Noboru Matsuda

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397

摘要： A semiconductor device comprises: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a trench formed in the second semiconductor region; a thick gate insulating film selectively provided in a center area of a bottom surface of the trench; a thin gate insulating film provided along a periphery of the bottom surface and on a sidewall of the trench; a third semiconductor region of the first conductivity type that is selectively provided below the thin gate insulating film provided along the periphery of the bottom surface of the trench and that extends to the first semiconductor region; a fourth semiconductor region of the first conductivity type selectively provided in the surface of the second semiconductor region; and a gate electrode filling the trench via the gate insulating film.

摘要翻译： 半导体器件包括：第一导电类型的第一半导体区域; 设置在第一半导体区域上的第二导电类型的第二半导体区域; 形成在第二半导体区域中的沟槽; 选择性地设置在沟槽的底面的中心区域的厚栅极绝缘膜; 沿着所述底表面的周边和所述沟槽的侧壁上设置的薄栅极绝缘膜; 第一导电类型的第三半导体区域，其被选择性地设置在沿着沟槽的底表面的周边设置并延伸到第一半导体区域的薄栅极绝缘膜的下方; 选择性地设置在第二半导体区域的表面中的第一导电类型的第四半导体区域; 以及通过栅极绝缘膜填充沟槽的栅电极。

公开(公告)号：US09214130B2

公开(公告)日：2015-12-15

申请号：US12735701

申请日：2009-01-19

申请人： Noboru Matsuda ,  Takahiro Yamaguchi ,  Isao Takahashi

发明人： Noboru Matsuda ,  Takahiro Yamaguchi ,  Isao Takahashi

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G5/006 ,  G09G3/3614 ,  G09G3/3655 ,  G09G3/3674 ,  G09G3/3685 ,  G09G2300/0857 ,  G09G2310/027 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2370/04

摘要： A display device of at least one embodiment of the present invention is a display device of an active matrix type, and includes a display driver supplied with image data included in serial data by serial transmission. The serial data is provided with a first flag for specifying a polarity of voltage of a common electrode. The display driver extracts the first flag from the serial data in accordance with a timing of a serial clock, and performs display in accordance with the image data, while generating the voltage of the common electrode which voltage has the polarity specified by the first flag extracted. This realizes a display device capable of generating a timing signal for AC common voltage, while having a small circuit.

摘要翻译： 本发明的至少一个实施例的显示装置是有源矩阵型的显示装置，并且包括通过串行传输提供包括在串行数据中的图像数据的显示驱动器。 串行数据被提供有用于指定公共电极的电压的极性的第一标志。 显示驱动器根据串行时钟的定时从串行数据提取第一标志，并且在产生具有由提取的第一标志指定的极性的电压的公共电极的电压的同时执行根据图像数据的显示 。 这实现了能够产生用于AC公共电压的定时信号的显示装置，同时具有小的电路。