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    Semiconductor device having two distinct sioch layers
    3.
    发明授权
    Semiconductor device having two distinct sioch layers 失效
    半导体器件具有两个不同的透镜层

    公开(公告)号：US07132732B2

    公开(公告)日：2006-11-07

    申请号：US10767786

    申请日：2004-01-29

    申请人： Koichi Ohto ,  Tatsuya Usami ,  Noboru Morita ,  Sadayuki Ohnishi ,  Koji Arita ,  Ryohei Kitao ,  Yoichi Sasaki

    发明人： Koichi Ohto ,  Tatsuya Usami ,  Noboru Morita ,  Sadayuki Ohnishi ,  Koji Arita ,  Ryohei Kitao ,  Yoichi Sasaki

    IPC分类号： H01L23/58 ,  H01L23/48

    CPC分类号： H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device has a semiconductor substrate, and a multi-layered wiring arrangement provided thereon. The multi-layered wring arrangement includes at least one insulating layer structure having a metal wiring pattern formed therein. The insulating layer structure includes a first SiOCH layer, a second SiOCH layer formed on the first SiOCH layer, and a silicon dioxide (SiO2) layer formed on the second SiOCH layer. The second SiOCH layer features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer, and an oxygen (O) density higher than that of the first SiOCH layer.

    摘要翻译： 半导体器件具有半导体衬底和设置在其上的多层布线装置。 多层绞合装置包括其中形成有金属布线图案的至少一个绝缘层结构。 绝缘层结构包括第一SiOCH层，形成在第一SiOCH层上的第二SiOCH层和形成在第二SiOCH层上的二氧化硅（SiO 2）层。 第二SiOCH层的碳（C）密度低于第一SiOCH层的碳（C）密度，氢（H）密度低于第一SiOCH层的密度，氧（O）密度高于第一SiOCH层 。

    Manufacturing method of semiconductor device
    4.
    发明授权
    Manufacturing method of semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US07563705B2

    公开(公告)日：2009-07-21

    申请号：US11359393

    申请日：2006-02-23

    申请人： Takashi Tonegawa ,  Koji Arita ,  Tatsuya Usami ,  Noboru Morita ,  Koichi Ohto ,  Yoichi Sasaki ,  Sadayuki Ohnishi ,  Ryohei Kitao

    发明人： Takashi Tonegawa ,  Koji Arita ,  Tatsuya Usami ,  Noboru Morita ,  Koichi Ohto ,  Yoichi Sasaki ,  Sadayuki Ohnishi ,  Ryohei Kitao

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76843 ,  H01L21/32051 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A manufacturing method of a semiconductor device including a step of forming a via hole in an insulation layer including an organic low dielectric film, such as MSQ, SiC, and SiCN, and then embedding a wiring material in the via hole through a barrier metal. According to this method, a plasma treatment is performed after the via hole is formed and before the barrier metal is deposited, using a He/H2 gas capable of replacing groups (methyl groups) made of organic constituents and covering the surface of the exposed organic low dielectric film (MSQ) with hydrogen, or a He gas capable decomposing the groups (methyl groups) without removing organic low dielectric molecules. As a result, the surface of the low dielectric film (MSQ) is reformed to be hydrophilic and adhesion to the barrier metal is hence improved, thereby making it possible to prevent the occurrence of separation of the barrier metal and scratches.

    摘要翻译： 一种半导体器件的制造方法，包括在包括诸如MSQ，SiC和SiCN的有机低电介质膜的绝缘层中形成通孔的步骤，然后通过阻挡金属将布线材料包埋在通孔中。 根据该方法，使用能够代替由有机成分构成的基团（甲基）并覆盖暴露的有机物的表面的He / H 2气体，在形成通孔并且在阻挡金属沉积之前进行等离子体处理 具有氢的低介电膜（MSQ）或能够分解基团（甲基）而不去除有机低介电分子的He气体。 结果，低电介质膜（MSQ）的表面被重新形成为亲水性，因此提高了与阻挡金属的粘合性，从而可以防止隔离金属的分离和划痕的发生。

    Manufacturing method of semiconductor device
    6.
    发明申请
    Manufacturing method of semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US20060141778A1

    公开(公告)日：2006-06-29

    申请号：US11359393

    申请日：2006-02-23

    申请人： Takashi Tonegawa ,  Koji Arita ,  Tatsuya Usami ,  Noboru Morita ,  Koichi Ohto ,  Yoichi Sasaki ,  Sadayuki Ohnishi ,  Ryohei Kitao

    发明人： Takashi Tonegawa ,  Koji Arita ,  Tatsuya Usami ,  Noboru Morita ,  Koichi Ohto ,  Yoichi Sasaki ,  Sadayuki Ohnishi ,  Ryohei Kitao

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76843 ,  H01L21/32051 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A manufacturing method of a semiconductor device including a step of forming a via hole in an insulation layer including an organic low dielectric film, such as MSQ, SiC, and SiCN, and then embedding a wiring material in the via hole through a barrier metal. According to this method, a plasma treatment is performed after the via hole is formed and before the barrier metal is deposited, using a He/H2 gas capable of replacing groups (methyl groups) made of organic constituents and covering the surface of the exposed organic low dielectric film (MSQ) with hydrogen, or a He gas capable decomposing the groups (methyl groups) without removing organic low dielectric molecules. As a result, the surface of the low dielectric film (MSQ) is reformed to be hydrophilic and adhesion to the barrier metal is hence improved, thereby making it possible to prevent the occurrence of separation of the barrier metal and scratches.

    摘要翻译： 一种半导体器件的制造方法，包括在包括诸如MSQ，SiC和SiCN的有机低电介质膜的绝缘层中形成通孔的步骤，然后通过阻挡金属将布线材料包埋在通孔中。 根据该方法，使用能够代替由有机成分构成的基团（甲基）的He / H 2气体，在形成通路孔之后和隔离金属沉积之前进行等离子体处理 并用氢气覆盖暴露的有机低介电膜（MSQ）的表面，或者能够分解基团（甲基）而不去除有机低介电分子的He气体。 结果，低电介质膜（MSQ）的表面被重新形成为亲水性，因此提高了与阻挡金属的粘附性，从而可以防止隔离金属的分离和划痕的发生。

    Method of manufacturing semiconductor device having damascene interconnection
    7.
    发明授权
    Method of manufacturing semiconductor device having damascene interconnection 有权
    制造具有镶嵌互连的半导体器件的方法

    公开(公告)号：US06989328B2

    公开(公告)日：2006-01-24

    申请号：US10777198

    申请日：2004-02-13

    申请人： Koji Arita ,  Kaoru Mikagi ,  Ryohei Kitao

    发明人： Koji Arita ,  Kaoru Mikagi ,  Ryohei Kitao

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76877 ,  H01L21/2885

    摘要： In copper plating using a damascene method, in order to prevent cost rise, dishing, erosion and the like due to the protrusion of plating on the dense wiring area to increase the time for CMP polishing, the copper plating is performed so that the current step of the copper plating has only one step for flowing current in the direction opposite to the direction of growing the plating as shown in FIG. 1. In this time, this opposite direction current step is performed under the condition of a current-time product within a range between 1.0 and 120 mA×sec/cm2.

    摘要翻译： 在使用镶嵌方法的镀铜中，为了防止由于在致密配线区域上的电镀突出而引起的成本上升，凹陷，侵蚀等，以增加CMP抛光的时间，进行镀铜，使得电流步骤 的铜电镀仅在与电镀方向相反的方向流动电流的一个步骤，如图3所示。 1。 此时，在1.0〜120mA / sec / cm 2范围内的当前时间积的条件下进行该相反方向电流步骤。

    Method of fabricating semiconductor device, and plating apparatus
    8.
    发明授权
    Method of fabricating semiconductor device, and plating apparatus 有权
    制造半导体器件的方法和电镀设备

    公开(公告)号：US08038864B2

    公开(公告)日：2011-10-18

    申请号：US11829129

    申请日：2007-07-27

    申请人： Koji Arita ,  Ryohei Kitao

    发明人： Koji Arita ,  Ryohei Kitao

    IPC分类号： C25D21/12

    CPC分类号： C25D21/12 ,  H01L21/2885 ,  H01L21/76877

    摘要： A method of fabricating a semiconductor device of the invention includes a plating process of filling a plurality of recesses provided to an insulating film formed on a substrate with an electro-conductive material, wherein the plating process includes a process step (S104) of performing the plating with a first current density which was obtained by correcting a predetermined first reference current density based on ratio of surface area Sr=S1/S2 of a first surface area S1 over the entire surface of the substrate which includes the area of side walls of the plurality of recesses over the entire surface of the semiconductor substrate, and a second surface area S2 over the entire surface of the substrate which does not include the area of side walls of the plurality of recesses, when fine recesses not larger than a predetermined width, out of all of the plurality of recesses, are filled with the electro-conductive material.

    摘要翻译： 制造本发明的半导体器件的方法包括：用导电材料填充设置在形成在基板上的绝缘膜的多个凹槽的电镀工艺，其中所述电镀工艺包括执行步骤（S104）的工艺步骤（S104） 以第一电流密度进行电镀，该第一电流密度通过基于第一表面积S1的表面积Sr = S1 / S2在衬底的整个表面上的比率校正预定的第一参考电流密度而得到，该第一电流密度包括 在半导体基板的整个表面上的多个凹部和在不包括多个凹部的侧壁的区域的基板的整个表面上的第二表面区域S2，当不大于预定宽度的细凹槽时， 在所有多个凹部中，填充有导电材料。

    Method of manufacturing a semiconductor device
    9.
    发明授权
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07229916B2

    公开(公告)日：2007-06-12

    申请号：US10892352

    申请日：2004-07-16

    申请人： Ryohei Kitao ,  Koji Arita

    发明人： Ryohei Kitao ,  Koji Arita

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/2885 ,  H01L21/76877

    摘要： A method of manufacturing a semiconductor device is to be provided, which improves filling performance of a conductive layer to be formed by an electrolytic plating process in an interconnect trench or a via hole, and achieves a higher in-plane uniformity in bottom-up performance. An electrolytic plating process to fill with a conductive layer at least one of an interconnect trench and a via hole formed in a dielectric layer on a semiconductor substrate includes a first step of executing a plating operation under a predetermined integrated current density, which is a product of a current density representing a current value supplied per unit area of a plating solution containing a material which constitutes the conductive layer and a plating time, and a second step of executing a plating operation under a lower current density than that of the first step.

    摘要翻译： 提供一种制造半导体器件的方法，其提高了通过互连沟槽或通孔中的电解电镀工艺形成的导电层的填充性能，并且实现了自底向上性能的更高的面内均匀性 。 在半导体衬底上的电介质层中形成的互连沟槽和通路孔中的至少一个填充导电层的电解电镀工艺包括：以预定的积分电流密度执行电镀操作的第一步骤，该电镀操作是产品 电流密度，表示包含构成导电层的材料的电镀溶液的每单位面积的电流值和电镀时间，以及在比第一步骤低的电流密度下进行电镀操作的第二步骤。

    Method of manufacturing a semiconductor device
    10.
    发明申请
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20050048769A1

    公开(公告)日：2005-03-03

    申请号：US10892352

    申请日：2004-07-16

    申请人： Ryohei Kitao ,  Koji Arita

    发明人： Ryohei Kitao ,  Koji Arita

    IPC分类号： C25D7/12 ,  C25D21/12 ,  H01L21/288 ,  H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/2885 ,  H01L21/76877

    摘要： A method of manufacturing a semiconductor device is to be provided, which improves filling performance of a conductive layer to be formed by an electrolytic plating process in an interconnect trench or a via hole, and achieves a higher in-plane uniformity in bottom-up performance. An electrolytic plating process to fill with a conductive layer at least one of an interconnect trench and a via hole formed in a dielectric layer on a semiconductor substrate includes a first step of executing a plating operation under a predetermined integrated current density, which is a product of a current density representing a current value supplied per unit area of a plating solution containing a material which constitutes the conductive layer and a plating time, and a second step of executing a plating operation under a lower current density than that of the first step.

    摘要翻译： 提供一种制造半导体器件的方法，其提高了通过互连沟槽或通孔中的电解电镀工艺形成的导电层的填充性能，并且实现了自底向上性能的更高的面内均匀性 。 在半导体衬底上的电介质层中形成的互连沟槽和通路孔中的至少一个填充导电层的电解电镀工艺包括：以预定的积分电流密度执行电镀操作的第一步骤，该电镀操作是产品 电流密度，表示包含构成导电层的材料的电镀溶液的每单位面积的电流值和电镀时间，以及在比第一步骤低的电流密度下进行电镀操作的第二步骤。