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公开(公告)号：US08503222B2
公开(公告)日：2013-08-06
申请号：US13144480
申请日：2010-01-21
申请人： Tetsuhiro Suzuki , Shunsuke Fukami , Kiyokazu Nagahara , Nobuyuki Ishiwata , Tadahiko Sugibayashi , Noboru Sakimura , Ryusuke Nebashi
发明人： Tetsuhiro Suzuki , Shunsuke Fukami , Kiyokazu Nagahara , Nobuyuki Ishiwata , Tadahiko Sugibayashi , Noboru Sakimura , Ryusuke Nebashi
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/5607 , H01L43/08 , H03K19/1776 , H03K19/1778 , H03K19/18 , H03K19/20
摘要： A non-volatile logic circuit includes an input section, a control section and an output section. The input section has perpendicular magnetic anisotropy and has a ferromagnetic layer whose magnetization state is changeable. The control section includes a ferromagnetic layer. The output section is provided in a neighborhood of the input section and the control section and includes a magnetic tunnel junction element whose magnetization state is changeable. The magnetization state of the input section is changed based on the magnetization state. A magnetization state of the magnetic tunnel junction element of the output section which state is changed based on the magnetization state of the ferromagnetic material of the control section and the magnetization state of the ferromagnetic material of the input section.
摘要翻译： 非易失性逻辑电路包括输入部分，控制部分和输出部分。 输入部具有垂直的磁各向异性，并具有磁化状态可变的铁磁层。 控制部分包括铁磁层。 输出部分设置在输入部分和控制部分的附近，并且包括磁化状态可变的磁性隧道结元件。 基于磁化状态改变输入部的磁化状态。 输出部分的磁性隧道结元件的磁化状态基于控制部分的铁磁材料的磁化状态和输入部分的铁磁材料的磁化状态而改变。
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公开(公告)号：US08243502B2
公开(公告)日：2012-08-14
申请号：US12747951
申请日：2008-11-19
IPC分类号： G11C11/00
CPC分类号： G11C11/18 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , H01L27/226 , H01L43/08 , H03K3/45
摘要： A nonvolatile latch circuit includes: a latch circuit; a first magnetoresistance element and a second magnetoresistance element; and a current supply portion. The latch circuit temporarily holds data. Each of the first magnetoresistance element and the second magnetoresistance element includes a first magnetic layer and a second magnetic layer that are stacked with an insulating film sandwiched therebetween. The current supply portion complementarily changes magnetization states of the first magnetoresistance element and the second magnetoresistance element based on a state of the latch circuit. The first magnetic layer of the first magnetoresistance element and the first magnetic layer of the second magnetoresistance element are series-connected to each other in. The latch circuit has a function that brings data corresponding to the magnetization states to data held by the latch circuit.
摘要翻译： 非易失性锁存电路包括：锁存电路; 第一磁阻元件和第二磁阻元件; 和电流供应部分。 锁存电路暂时保存数据。 第一磁阻元件和第二磁阻元件中的每一个包括层叠有绝缘膜的第一磁性层和第二磁性层。 电流供应部分基于锁存电路的状态互补地改变第一磁阻元件和第二磁阻元件的磁化状态。 第一磁阻元件的第一磁性层和第二磁阻元件的第一磁性层彼此串联连接。锁存电路具有将对应于磁化状态的数据带入由锁存电路保持的数据的功能。
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公开(公告)号：US20100271866A1
公开(公告)日：2010-10-28
申请号：US12746589
申请日：2008-12-03
CPC分类号： H03K3/45 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/18 , G11C14/0081 , H01L27/11 , H03K3/356008 , Y10S977/933 , Y10S977/935
摘要： A nonvolatile latch circuit includes: first and second inverters cross-coupled to hold 1-bit data; first and second magnetoresistive elements each having first to third terminals; and a current supply circuitry configured to supply a magnetization reversal current for changing the magnetization states of the first and second maqnetoresistive elements in response to the 1-bit data. The power terminal of the first inverter is connected to the first terminal of the first magnetoresistive element and the power terminal of the second inverter is connected to the first terminal of the second magnetoresistive element. The current supply circuitry is configured to supply the magnetization reversal current to the second terminals of the first and second magnetoresistive elements. The third terminal of the first magnetoresistive element is electrically connected to the third terminal of the second magnetoresistive element.
摘要翻译： 非易失性锁存电路包括：交叉耦合以保持1位数据的第一和第二反相器; 第一和第二磁阻元件各自具有第一至第三端子; 以及电流源电路，被配置为响应于1位数据提供用于改变第一和第二电阻元件的磁化状态的磁化反转电流。 第一反相器的电源端子连接到第一磁阻元件的第一端子，第二反相器的电源端子连接到第二磁阻元件的第一端子。 电流供应电路被配置为向第一和第二磁阻元件的第二端提供磁化反转电流。 第一磁阻元件的第三端子电连接到第二磁阻元件的第三端子。
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公开(公告)号：US20100265760A1
公开(公告)日：2010-10-21
申请号：US12747951
申请日：2008-11-19
CPC分类号： G11C11/18 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , H01L27/226 , H01L43/08 , H03K3/45
摘要： A nonvolatile latch circuit includes: a latch circuit; a first magnetoresistance element and a second magnetoresistance element; and a current supply portion. The latch circuit temporarily holds data. Each of the first magnetoresistance element and the second magnetoresistance element includes a first magnetic layer and a second magnetic layer that are stacked with an insulating film sandwiched therebetween. The current supply portion complementarily changes magnetization states of the first magnetoresistance element and the second magnetoresistance element based on a state of the latch circuit. The first magnetic layer of the first magnetoresistance element and the first magnetic layer of the second magnetoresistance element are series-connected to each other in. The latch circuit has a function that brings data corresponding to the magnetization states to data held by the latch circuit.
摘要翻译： 非易失性锁存电路包括：锁存电路; 第一磁阻元件和第二磁阻元件; 和电流供应部分。 锁存电路暂时保存数据。 第一磁阻元件和第二磁阻元件中的每一个包括层叠有绝缘膜的第一磁性层和第二磁性层。 电流供应部分基于锁存电路的状态互补地改变第一磁阻元件和第二磁阻元件的磁化状态。 第一磁阻元件的第一磁性层和第二磁阻元件的第一磁性层彼此串联连接。锁存电路具有将对应于磁化状态的数据带入由锁存电路保持的数据的功能。
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公开(公告)号：US20130182501A1
公开(公告)日：2013-07-18
申请号：US13824888
申请日：2011-12-06
CPC分类号： H01L27/228 , G11C11/161 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C2213/74 , G11C2213/79 , H01L43/12
摘要： A magnetoresistive element 10 having a memory cell 100 according to the present invention contains a first lower terminal n1 and a second lower terminal n2 respectively connected to both ends of a conductive layer 3 whose longitudinal direction is different from the column direction (X direction). Further, the gates of the first transistors M1 respectively included in two memory cells among the plurality of memory cells 100 and adjacent to each other in a row direction (Y direction) are commonly connected to a first word line 14. As a result, without increase of the cell area, it becomes possible to reserve a margin in the dimension of the cell structure or in the process for MRMA.
摘要翻译： 具有根据本发明的存储单元100的磁阻元件10包含分别连接到纵向方向不同于列方向（X方向）的导电层3的两端的第一下端子n1和第二下端子n2。 此外，分别包括在多个存储单元100中并且在行方向（Y方向）上彼此相邻的两个存储单元中的第一晶体管M1的栅极共同连接到第一字线14.结果，没有 增加单元面积，可以在单元结构的尺寸或MRMA的处理中保留余量。
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公开(公告)号：US08174872B2
公开(公告)日：2012-05-08
申请号：US12746589
申请日：2008-12-03
IPC分类号： G11C11/00
CPC分类号： H03K3/45 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/18 , G11C14/0081 , H01L27/11 , H03K3/356008 , Y10S977/933 , Y10S977/935
摘要： A nonvolatile latch circuit includes: first and second inverters cross-coupled to hold 1-bit data; first and second magnetoresistive elements each having first to third terminals; and a current supply circuitry configured to supply a magnetization reversal current for changing the magnetization states of the first and second maqnetoresistive elements in response to the 1-bit data. The power terminal of the first inverter is connected to the first terminal of the first magnetoresistive element and the power terminal of the second inverter is connected to the first terminal of the second magnetoresistive element. The current supply circuitry is configured to supply the magnetization reversal current to the second terminals of the first and second magnetoresistive elements. The third terminal of the first magnetoresistive element is electrically connected to the third terminal of the second magnetoresistive element.
摘要翻译： 非易失性锁存电路包括：交叉耦合以保持1位数据的第一和第二反相器; 第一和第二磁阻元件各自具有第一至第三端子; 以及电流源电路，被配置为响应于1位数据提供用于改变第一和第二电阻元件的磁化状态的磁化反转电流。 第一反相器的电源端子连接到第一磁阻元件的第一端子，第二反相器的电源端子连接到第二磁阻元件的第一端子。 电流供应电路被配置为向第一和第二磁阻元件的第二端提供磁化反转电流。 第一磁阻元件的第三端子电连接到第二磁阻元件的第三端子。
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7.发明申请NONVOLATILE RESISTOR NETWORK ASSEMBLY AND NONVOLATILE LOGIC GATE WITH INCREASED FAULT TOLERANCE USING THE SAME 有权非线性电阻网络组件和非易失性逻辑门，使用相同的增加的故障容限公开(公告)号：US20150042376A1
公开(公告)日：2015-02-12
申请号：US14344446
申请日：2012-09-06
IPC分类号： H03K19/177 , G11C11/16
CPC分类号： H03K19/17764 , G11C11/16 , G11C11/1675 , G11C19/0808 , H03K19/1776 , H03K19/18
摘要： Provided is a nonvolatile resistor network assembly characterized by that: it comprises a first and a second resistor network which are each composed of a plurality of nonvolatile resistive elements connected together; it also comprises a write means for writing into the first and second resistor networks; and writing into the first and second resistor networks is performed by the use of the write means in a manner to make total resistances of respectively the first and second resistor networks different from each other. Further provided is a nonvolatile logic gate which performs logical operation using stored data determined by the total resistances of the respective nonvolatile resistor networks.
摘要翻译： 提供了一种非易失性电阻网络组件，其特征在于：它包括第一和第二电阻器网络，每个由连接在一起的多个非易失性电阻元件组成; 它还包括写入第一和第二电阻网络的写入装置; 并且通过使用写入装置以使得第一和第二电阻网络的总电阻彼此不同的方式来执行写入第一和第二电阻器网络的写入。 还提供了一种非易失性逻辑门，其使用由各个非易失性电阻网络的总电阻确定的存储数据执行逻辑运算。
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公开(公告)号：US08510633B2
公开(公告)日：2013-08-13
申请号：US12596243
申请日：2008-04-14
IPC分类号： G11C29/00
CPC分类号： G11C13/0007 , G06F11/1008 , G11C13/0004 , G11C13/0011 , G11C13/004 , G11C29/00 , G11C2013/0054 , G11C2029/0411
摘要： Provided is an operation method which can be applied to a PRAM, an ReRAM, and a solid electrolyte memory which stores error correction codes, each of which comprises of symbols, each of which comprises bits, and which codes allow error correction in units of symbols. In the operation method, the respective symbols are read by using different reference cells 12. When a correctable error is detected in read data from data cells forming the error correction codes and corresponding to an input address, a data in a data cell corresponding to the error bit is corrected for a first error symbol of an one bit error pattern, and data in a reference cell that is used to read the second error symbol are corrected for a second error symbol related to a multi-bit error pattern.
摘要翻译： 提供了可应用于PRAM，ReRAM和固体电解质存储器的操作方法，该存储器存储纠错码，每个都包括符号，每个符号包括位，并且哪些代码允许以符号为单位进行纠错 。 在操作方法中，通过使用不同的参考单元12来读取各个符号。当从形成纠错码的数据单元的读取数据中检测到可校正错误并对应于输入地址时，在与数据单元对应的数据单元中的数据 针对一位错误模式的第一错误符号校正错误位，并且对于与多位错误模式相关的第二错误符号来校正用于读取第二错误符号的参考单元中的数据。
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9.发明申请公开(公告)号：US20110148458A1
公开(公告)日：2011-06-23
申请号：US13060574
申请日：2009-08-12
CPC分类号： H01L43/08 , G11C11/161 , G11C11/1659 , G11C11/1675 , H01L43/12 , H03K19/168 , H03K19/18
摘要： A logic gate 40 according to the present invention has a magnetoresistive element 1, a magnetization state control unit 50 and an output unit 60. The magnetoresistive element 1 has a laminated structure having N (N is an integer not smaller than 3) magnetic layers 10 and N−1 nonmagnetic layers that are alternately laminated. A resistance value R of the magnetoresistive element 1 varies depending on magnetization states of the N magnetic layers 10. The magnetization state control unit 50 sets the respective magnetization states of the N magnetic layers 10 depending on N input data. The output unit 60 outputs an output data that varies depending on the resistance value R of the magnetoresistive element 1.
摘要翻译： 根据本发明的逻辑门40具有磁阻元件1，磁化状态控制单元50和输出单元60.磁阻元件1具有N（N是不小于3的整数）磁性层10的层叠结构 和N-1个非磁性层。 磁阻元件1的电阻值R根据N个磁性层10的磁化状态而变化。磁化状态控制单元50根据N个输入数据来设定N个磁性层10的各自的磁化状态。 输出单元60输出根据磁阻元件1的电阻值R而变化的输出数据。
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公开(公告)号：US20110016371A1
公开(公告)日：2011-01-20
申请号：US12596243
申请日：2008-04-14
CPC分类号： G11C13/0007 , G06F11/1008 , G11C13/0004 , G11C13/0011 , G11C13/004 , G11C29/00 , G11C2013/0054 , G11C2029/0411
摘要： Provided is an operation method which can be applied to a PRAM, an ReRAM, and a solid electrolyte memory which stores error correction codes, each of which comprises of symbols, each of which comprises bits, and which codes allow error correction in units of symbols. In the operation method, the respective symbols are read by using different reference cells 12. When a correctable error is detected in read data from data cells forming the error correction codes and corresponding to an input address, a data in a data cell corresponding to the error bit is corrected for a first error symbol of an one bit error pattern, and data in a reference cell that is used to read the second error symbol are corrected for a second error symbol related to a multi-bit error pattern.
摘要翻译： 提供了可应用于PRAM，ReRAM和固体电解质存储器的操作方法，该存储器存储纠错码，每个都包括符号，每个符号包括位，并且哪些代码允许以符号为单位进行纠错 。 在操作方法中，通过使用不同的参考单元12来读取各个符号。当从形成纠错码的数据单元的读取数据中检测到可校正错误并对应于输入地址时，在与数据单元对应的数据单元中的数据 针对一位错误模式的第一错误符号校正错误位，并且对于与多位错误模式相关的第二错误符号来校正用于读取第二错误符号的参考单元中的数据。
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