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    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20120248602A1

    公开(公告)日：2012-10-04

    申请号：US13494537

    申请日：2012-06-12

    申请人： Nobuaki TAKAHASHI ,  Masahiro KOMURO ,  Satoshi MATSUI

    发明人： Nobuaki TAKAHASHI ,  Masahiro KOMURO ,  Satoshi MATSUI

    IPC分类号： H01L23/48

    CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05684 ,  H01L2224/13009 ,  H01L2224/131 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/17181 ,  H01L2924/00014

    摘要： In this semiconductor device, the through-hole is formed in the substrate, and is located under the conductive pattern. The insulating layer is located at the bottom surface of the through-hole. The conductive pattern is located on one surface side of the substrate. The opening pattern is formed in the insulating layer which is located between the through-hole and the conductive pattern, where the distance r3 from the circumference of the opening pattern to the central axis of the through-hole is smaller than the distance r1 in the through-hole. By providing the opening pattern, the conductive pattern is exposed at the bottom surface of the through-hole. The bump is located on the back surface side of the substrate, and is formed integrally with the through-electrode.

    摘要翻译： 在该半导体装置中，通孔形成在基板上，位于导电图案的下方。 绝缘层位于通孔的底面。 导电图案位于基板的一个表面侧。 开口图案形成在位于通孔和导电图案之间的绝缘层中，其中从开口图案的周边到通孔的中心轴线的距离r3小于通孔中的距离r1 通孔。 通过设置开口图案，导电图案在通孔的底面露出。 凸块位于基板的背面侧，与贯通电极一体形成。

    SEMICONDUCTOR ELEMENT-EMBEDDED WIRING SUBSTRATE
    3.
    发明申请
    SEMICONDUCTOR ELEMENT-EMBEDDED WIRING SUBSTRATE 审中-公开
    半导体元件嵌入式基板

    公开(公告)号：US20110215478A1

    公开(公告)日：2011-09-08

    申请号：US13040021

    申请日：2011-03-03

    申请人： Shintaro YAMAMICHI ,  Hideya MURAI ,  Kentaro MORI ,  Katsumi KIKUCHI ,  Yoshiki NAKASHIMA ,  Masaya KAWANO ,  Masahiro KOMURO

    发明人： Shintaro YAMAMICHI ,  Hideya MURAI ,  Kentaro MORI ,  Katsumi KIKUCHI ,  Yoshiki NAKASHIMA ,  Masaya KAWANO ,  Masahiro KOMURO

    IPC分类号： H01L23/522

    CPC分类号： H01L23/522 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

    摘要： In a wiring substrate containing a semiconductor element, the wiring substrate includes a supporting substrate; a semiconductor element provided on the supporting substrate; a peripheral insulating layer covering at least an outer circumferential side surface of the semiconductor element; and upper surface-side wiring provided on the upper surface side of the wiring substrate. The semiconductor element includes a semiconductor substrate; a first wiring-structure layer including first wiring and a first insulating layer alternately formed on the semiconductor substrate; and a second wiring-structure layer including second wiring and a second insulating layer alternately formed on the first wiring-structure layer. The upper surface-side wiring includes fan-out wiring led out from immediately above the semiconductor element to a peripheral region external to an outer edge of the semiconductor element. The fan-out wiring is electrically connected to the first wiring through the second wiring. The second wiring is thicker than the first wiring but thinner than the upper surface-side wiring. The second insulating layer is formed of a resin material and is thicker than the first insulating layer.

    摘要翻译： 在包含半导体元件的布线基板中，布线基板包括支撑基板; 设置在所述支撑基板上的半导体元件; 覆盖半导体元件的至少外周侧表面的外围绝缘层; 以及设置在布线基板的上表面侧的上表面侧布线。 半导体元件包括半导体衬底; 第一布线结构层，包括交替形成在所述半导体衬底上的第一布线和第一绝缘层; 以及第二布线结构层，包括交替地形成在第一布线结构层上的第二布线和第二绝缘层。 上表面侧布线包括从半导体元件的正上方引导到半导体元件的外边缘外围的外围区域的扇出布线。 扇出布线通过第二布线电连接到第一布线。 第二布线比第一布线厚，但比上表面布线薄。 第二绝缘层由树脂材料形成，并且比第一绝缘层厚。