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83 条记录 (耗时 0.035 秒)

    Multichannel record disc reproducing system
    1.
    发明授权
    Multichannel record disc reproducing system 失效
    多通道记录盘再现系统

    公开(公告)号：US3991283A

    公开(公告)日：1976-11-09

    申请号：US612640

    申请日：1975-09-12

    申请人： Yasuo Itoh ,  Nobuaki Takahashi ,  Masao Kasuga

    发明人： Yasuo Itoh ,  Nobuaki Takahashi ,  Masao Kasuga

    IPC分类号： G11B23/00 ,  H03G5/18 ,  H03G7/00 ,  G11B3/00 ,  G11B3/74

    CPC分类号： G11B23/0007 ,  H03G5/18 ,  H03G7/00

    摘要： A multichannel record disc reproducing system comprises a circuit for demodulating an angle-modulated wave picked up from a multichannel record disc. A circuit detects abnormal phenomena of the angle-modulated wave, whereupon an expansion circuit accomplishes a variable control operation. A middle frequency band and/or a high frequency band component of the demodulated signal is attenuated in accordance with the level thereof. A circuit is operated in response to the output of the detection circuit to stop a variable expansion control operation of the expansion circuit and imparts a specific attenuation characteristic to a signal passing through the expansion circuit.

    摘要翻译： 多声道记录盘重放系统包括用于解调从多声道记录盘拾取的角度调制波的电路。 电路检测角度调制波的异常现象，由此扩展电路实现可变控制操作。 解调信号的中频带和/或高频带分量根据其电平被衰减。 响应于检测电路的输出来操作电路以停止扩展电路的可变扩展控制操作，并且对通过扩展电路的信号赋予特定的衰减特性。

    Angle modulated wave demodulation system
    2.
    发明授权
    Angle modulated wave demodulation system 失效
    角度调制波解调系统

    公开(公告)号：US3934087A

    公开(公告)日：1976-01-20

    申请号：US403635

    申请日：1973-10-04

    申请人： Nobuaki Takahashi ,  Yoshiki Iwasaki ,  Masao Kasuga ,  Yasuo Itoh

    发明人： Nobuaki Takahashi ,  Yoshiki Iwasaki ,  Masao Kasuga ,  Yasuo Itoh

    IPC分类号： H03D3/24 ,  H04S3/00 ,  G11B3/04

    CPC分类号： H04S3/006 ,  H03D3/244

    摘要： A system for demodulating angle modulated waves comprises a phase locked loop including a phase comparator and a voltage controlled oscillator. An attenuation means is inserted into the phase locked loop. This attenuation means does not affect the DC component of an input angle modulated wave, but does cause an attenuation with respect to an AC component, to cause a decrease in the loop gain. The phase locked loop has a DC lock range exhibiting a relatively wide lock range width even when the input level is relatively low and an AC lock range produced by the attenuation circuit and exhibiting a relatively narrow lock range width when the input level is relatively low. The attenuation means detects an abnormality in the angle modulated wave, the harmonics component of the direct wave, and the like. A variable attenuation circuit controlled by the output of the detecting means is varied in its attenuation quantity.

    摘要翻译： 用于解调角度调制波的系统包括包括相位比较器和压控振荡器的锁相环。 衰减装置插入到锁相环中。 该衰减装置不影响输入角调制波的直流分量，但是相对于AC分量产生衰减，导致环路增益的降低。 即使当输入电平相对较低时，锁相环也具有相对宽的锁定范围宽度的DC锁定范围，并且当输入电平相对较低时，锁相环由衰减电路产生并产生相对窄的锁定范围宽度。 衰减装置检测角度调制波的异常，直接波的谐波分量等。 由检测装置的输出控制的可变衰减电路的衰减量变化。

    Matrix and equalizer circuit with gain control
    3.
    发明授权
    Matrix and equalizer circuit with gain control 失效
    具有增益控制的矩阵和均衡器电路

    公开(公告)号：US3983334A

    公开(公告)日：1976-09-28

    申请号：US551733

    申请日：1975-02-21

    申请人： Nobuaki Takahashi ,  Yasuo Itoh ,  Masao Kasuga

    发明人： Nobuaki Takahashi ,  Yasuo Itoh ,  Masao Kasuga

    IPC分类号： H03F3/68 ,  G11B3/00 ,  H04S3/00 ,  G11B3/74

    CPC分类号： H04S3/006

    摘要： A combined matrix and equalizer circuit comprises a matrix circuit for operating with gains on a plurality of input signals. A feedback loop feeds back from a point between output terminals of the matrix circuit and a specific one of the input terminals of the same circuit. The feedback loop causes a signal entering a specific input terminal to have a specific equalizing frequency characteristic.

    摘要翻译： 组合矩阵和均衡器电路包括用于在多个输入信号上进行增益的矩阵电路。 反馈环路从矩阵电路的输出端子和同一电路的特定输入端子之间的点反馈。 反馈回路使得进入特定输入端的信号具有特定的均衡频率特性。

    Composite filter circuit
    4.
    发明授权
    Composite filter circuit 失效
    复合滤波电路

    公开(公告)号：US3944755A

    公开(公告)日：1976-03-16

    申请号：US550376

    申请日：1975-02-18

    申请人： Nobuaki Takahashi ,  Masao Kasuga ,  Yasuo Itoh

    发明人： Nobuaki Takahashi ,  Masao Kasuga ,  Yasuo Itoh

    IPC分类号： G11B3/00 ,  H03H7/01 ,  H03H7/46 ,  H04S3/00 ,  G11B3/74 ,  H03H5/06

    CPC分类号： H03H7/06 ,  H03H7/1766 ,  H03H7/463 ,  H04S3/006 ,  H03H7/075

    摘要： A composite filter circuit comprises a first series resonant circuit connected to a single common resistor, resonating at a first frequency, and exhibiting a low-pass filtering characteristic. A parallel resonant circuit includes one circuit element of the first series resonant circuit and resonates at a second frequency. A second series resonant circuit is connected to the single common resistor, resonating at the second frequency, and exhibiting a highpass filtering characteristic. The first series resonant circuit and the parallel resonant circuit constitute a low-pass filter circuit section. This low-pass filtering characteristic results from the total effects of the low-pass filtering characteristic of the first series resonant circuit, a dip characteristic of the parallel resonant circuit, and, in addition, a decreasing characteristic at the second frequency, due to the second series resonant circuit. The second series resonant circuit constitutes a high-pass or band-pass filter circuit section having a high-pass filtering characteristic resulting from the total effect of the high-pass filtering characteristic of the second series resonant circuit and, in addition, the decreasing characteristic at the first frequency due to the first series resonant circuit.

    摘要翻译： 复合滤波器电路包括连接到单个公共电阻器的第一串联谐振电路，以第一频率谐振并呈现低通滤波特性。 并联谐振电路包括第一串联谐振电路的一个电路元件并以第二频率谐振。 第二串联谐振电路连接到单个公共电阻器，在第二频率处谐振并呈现高通滤波特性。 第一串联谐振电路和并联谐振电路构成低通滤波电路部分。 该低通滤波特性是由于第一串联谐振电路的低通滤波特性，并联谐振电路的下降特性以及第二频率的降低特性的总效应，由于 第二串联谐振电路。 第二串联谐振电路构成由第二串联谐振电路的高通滤波特性的总效应导致的具有高通滤波特性的高通或带通滤波器电路部分，此外，降低特性 由于第一串联谐振电路在第一频率。

    Non-volatile semiconductor memory device for storing multivalue data and readout/write-in method therefor
    10.
    发明授权
    Non-volatile semiconductor memory device for storing multivalue data and readout/write-in method therefor 失效
    用于存储多值数据和其读出/写入方法的非易失性半导体存储器件

    公开(公告)号：US5751634A

    公开(公告)日：1998-05-12

    申请号：US647629

    申请日：1996-05-15

    申请人： Yasuo Itoh

    发明人： Yasuo Itoh

    IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C7/00

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5642 ,  G11C2211/5647

    摘要： Memory cells each for storing 2-bit data are connected to a bit line. First and second flip-flop circuits are coupled to the bit line. The first flip-flop circuit holds the lower bit of 2-bit data read out from or written into the memory cell and the second flip-flop circuit holds the upper bit of 2-bit data read out from or written into the memory cell. At the data readout time, the upper bit is first read out from the memory cell and then the lower bit is read out from the memory cell. At the data writing time, the upper bit is first written into the memory cell and then the lower bit is written into the memory cell.

    摘要翻译： 每个用于存储2位数据的存储单元连接到位线。 第一和第二触发器电路耦合到位线。 第一触发器电路保持从存储单元读出或写入存储单元的2位数据的低位，并且第二触发器电路保持从存储单元读出或写入存储单元的2位数据的高位。 在数据读出时，首先从存储单元读出高位，然后从存储单元读出低位。 在数据写入时，首先将高位写入存储单元，然后将较低位写入存储单元。