公开(公告)号：US5324982A

公开(公告)日：1994-06-28

申请号：US769680

申请日：1991-10-02

申请人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

发明人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L27/04 ,  H01L29/70

CPC分类号： H01L27/10805 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/0218 ,  H01L27/105 ,  Y10S257/901 ,  Y10S257/904

摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

摘要翻译： 公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域， 在另一。

公开(公告)号：US5026654A

公开(公告)日：1991-06-25

申请号：US159925

申请日：1988-02-24

申请人： Nobuo Tanba ,  Takahide Ikeda

发明人： Nobuo Tanba ,  Takahide Ikeda

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/73

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L21/8249 ,  H01L27/0623

摘要： Disclosed is here a semicondutor integrated circuit device and a method of manufacturing the same in which bipolar transistors and MISFETs are formed on a semiconductor substrate. Emitter and base electrodes of the bipolar transistors and gate, source, and drain electrodes of the MISFETs are constituted with the same polycrystalline layer, thereby realizing a high integration and a high-speed operation of a Bi-CMOS device.

摘要翻译： 这里公开了半导体集成电路器件及其制造方法，其中双极晶体管和MISFET形成在半导体衬底上。 双极晶体管的发射极和基极和MISFET的栅极，源极和漏极都由相同的多晶层构成，从而实现了Bi-CMOS器件的高集成度和高​​速工作。

公开(公告)号：US06208010B1

公开(公告)日：2001-03-27

申请号：US08574110

申请日：1995-12-18

申请人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

发明人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

IPC分类号： H01L2900

CPC分类号： H01L27/10805 ,  H01L27/0214 ,  H01L27/0218 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/105 ,  Y10S257/901 ,  Y10S257/904

摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

摘要翻译： 公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域， 在另一。

公开(公告)号：US06740958B2

公开(公告)日：2004-05-25

申请号：US10115101

申请日：2002-04-04

申请人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

发明人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

IPC分类号： H01L2900

CPC分类号： H01L27/0623 ,  H01L27/0214 ,  H01L27/0218 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/10805

摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

摘要翻译： 公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域， 在另一。

公开(公告)号：US5386135A

公开(公告)日：1995-01-31

申请号：US229340

申请日：1994-04-12

申请人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

发明人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10805 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/0218 ,  H01L27/105 ,  Y10S257/901 ,  Y10S257/904

摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

摘要翻译： 公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域， 在另一。

公开(公告)号：US5148255A

公开(公告)日：1992-09-15

申请号：US645351

申请日：1991-01-23

申请人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

发明人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/10805 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/0218 ,  H01L27/105

摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

摘要翻译： 公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域， 在另一。

公开(公告)号：US06864559B2

公开(公告)日：2005-03-08

申请号：US10377717

申请日：2003-03-04

申请人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

发明人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/00

CPC分类号： H01L27/0623 ,  H01L27/0214 ,  H01L27/0218 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/10805

摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

摘要翻译： 公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域， 在另一。

公开(公告)号：US5497023A

公开(公告)日：1996-03-05

申请号：US352238

申请日：1994-12-08

申请人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikasu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

发明人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikasu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10805 ,  H01L27/0214 ,  H01L27/0623 ,  H01L27/0922 ,  H01L27/0218 ,  H01L27/105 ,  Y10S257/901 ,  Y10S257/904

摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

摘要翻译： 公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域， 在另一。

公开(公告)号：US5793097A

公开(公告)日：1998-08-11

申请号：US519096

申请日：1995-08-24

申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

IPC分类号： H01C7/06 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L29/00 ,  H01L23/48 ,  H01L29/76

CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二 多晶层具有负电阻的温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

公开(公告)号：US4377421A

公开(公告)日：1983-03-22

申请号：US186743

申请日：1980-09-12

申请人： Yasuo Wada ,  Takahide Ikeda ,  Masao Tamura

发明人： Yasuo Wada ,  Takahide Ikeda ,  Masao Tamura

IPC分类号： H01L29/73 ,  H01L21/02 ,  H01L21/20 ,  H01L21/268 ,  H01L21/331 ,  H01L29/04 ,  H01L29/08 ,  H01L29/72 ,  H01L21/263

CPC分类号： H01L28/20 ,  H01L21/268 ,  H01L29/04 ,  H01L29/0804 ,  H01L29/72 ,  Y10S117/904 ,  Y10S148/092

摘要： An insulating film is formed on a semiconductor substrate, and the insulating film on that part of the semiconductor substrate where an emitter is to be formed, is removed to expose the surface of the above part. A polycrystalline or amorphous silicon film is deposited on the entire surface, and then irradiated with a laser beam to convert that portion of the polycrystalline or amorphous silicon film which is deposited on the surface of the semiconductor substrate without interposing the insulating film therebetween, into a single crystal of silicon, thereby forming a stacked emitter.

摘要翻译： 在半导体衬底上形成绝缘膜，并且去除要形成发射极的半导体衬底的那部分上的绝缘膜，以露出上述部分的表面。 多晶或非晶硅膜沉积在整个表面上，然后用激光束照射，以将沉积在半导体衬底的表面上的多晶硅或非晶硅膜的那部分转换成其间的绝缘膜， 硅单晶，从而形成堆叠的发射极。