公开(公告)号：US20170309566A1

公开(公告)日：2017-10-26

申请号：US15510360

申请日：2014-09-11

Applicant: Renesas Electronics Corporation

Inventor： Naotake WATANABE

IPC: H01L23/525 ,  H01L21/70 ,  G01R31/28 ,  H01L21/82 ,  H01L27/11 ,  H01L29/72

CPC classification number: H01L23/5256 ,  G01R31/28 ,  G01R31/2856 ,  G01R31/2896 ,  G01R31/318513 ,  H01L21/70 ,  H01L21/82 ,  H01L23/5383 ,  H01L27/11 ,  H01L29/72 ,  H01L2924/0002

Abstract: A semiconductor integrated circuit device (1000) includes: a first semiconductor chip CHP1 having a first circuit; and a second semiconductor chip (CHP2) having a second circuit and differing from the first semiconductor chip (CHP1). The semiconductor integrated circuit device (1000) further includes a control circuit (BTCNT) for controlling an operation of the first circuit and an operation of the second circuit in accordance with a control signal in a burn-in test, and the control circuit (BTCNT) controls the first circuit and the second circuit such that an amount of stress applied to the first semiconductor chip (CHP1) due to an operation of the first circuit and an amount of stress applied to the second semiconductor chip (CHP2) due to an operation of the second circuit differ from each other in the burn-in test.

公开(公告)号：US20160322484A1

公开(公告)日：2016-11-03

申请号：US15083217

申请日：2016-03-28

Applicant: Ideal Power Inc.

Inventor： Richard A. Blanchard

IPC: H01L29/747 ,  H01L29/40 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/0821 ,  H01L23/535 ,  H01L27/0694 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/402 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/72 ,  H01L29/735

Abstract: A symmetrically-bidirectional power bipolar transistor having, on both surfaces of a semiconductor die, an n-type emitter/collector region which is completely surrounded by a first recessed field plate, which is itself completely surrounded by a p-type region including p+ contact areas. All of the p-type region is preferably bordered and surrounded by a second recessed field plate trench. The second recessed field plate trench is itself surrounded by an n-type region which is wholly or partially made of the same diffusion as the emitter/collector regions, but which is not connected to the metallization which connects the emitter/collector regions to extermal terminals.

Abstract translation: 一种对称双向功率双极晶体管，其在半导体管芯的两个表面上具有由第一凹陷场板完全包围的n型发射极/集电极区域，其本身完全被包括p +接触的p型区域包围 地区 所有的p型区域优选地被边界界定并被第二凹陷场板沟槽包围。 第二凹陷场板沟槽本身被n型区域包围，该n型区域完全或部分地由与发射极/集电极区域相同的扩散部分构成，但是不连接到将发射极/集电极区域连接到外部端子的金属化 。

公开(公告)号：US09337262B2

公开(公告)日：2016-05-10

申请号：US14599191

申请日：2015-01-16

Applicant: Ideal Power Inc.

Inventor： Richard A. Blanchard

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/732 ,  H01L29/735

CPC classification number: H01L29/0619 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/402 ,  H01L29/404 ,  H01L29/72 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/747 ,  H03K17/66

Abstract: The present application provides (in addition to more broadly applicable inventions) improvements which are particularly applicable to two-sided power semiconductor devices which use bipolar conduction. In this class of devices, the inventor has realized that two or three of the four (or more) semiconductor doping components which form the carrier-emission structures and control structures in the active device (array) portion of a two-sided power device can also be used, with surprising advantages, to form field-limiting rings around the active arrays on both surfaces. Most preferably, in some but not necessarily all embodiments, a shallow implant of one conductivity type is used to counterdope the surface of a well having the other conductivity type. This shallow implant, singly or in combination with another shallow implant of the same conductivity type, works to shield the well from the effects of excess charge at or above the surface of the semiconductor material.

Abstract translation: 本申请提供了特别适用于使用双极性导通的双面功率半导体器件的（更广泛适用的发明）的改进。 在这类器件中，发明人已经意识到，在双面功率器件的有源器件（阵列）部分中形成载流子发射结构和控制结构的四个（或更多个）半导体掺杂元件中的两个或三个可以 也可以使用惊人的优点，在两个表面上的有源阵列周围形成限界环。 最优选地，在一些但不一定所有实施例中，使用一种导电类型的浅植入物来反射具有另一导电类型的阱的表面。 这种浅植入物，单独地或与另一种具有相同导电类型的浅植入物组合起作用，以防止阱受到半导体材料表面上或其上的过量电荷的影响。

公开(公告)号：US20140327017A1

公开(公告)日：2014-11-06

申请号：US14331515

申请日：2014-07-15

Applicant: Tom Nelson Oder

Inventor： Tom Nelson Oder

IPC: H01L29/16 ,  H01L29/47 ,  H01L29/872

CPC classification number: H01L29/1608 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/72 ,  H01L29/872

Abstract: Improved semiconductor devices are fabricated utilizing nickel gallide and refractory borides deposited onto a silicon carbide semiconductor substrate. Varying the deposition and annealing parameters of fabrication can provide a more thermally stable device that has greater barrier height and a low ideality. This improvement in the electrical properties allows use of Schottky barrier diodes in high power and high temperature applications. In one embodiment, a refractory metal boride layer is joined to a surface of a silicon carbide semiconductor substrate. The refractory metal boride layer is deposited on the silicon carbon semiconductor substrate at a temperature greater than 200° C. In another embodiment, a Schottky barrier diode is fabricated via deposition of nickel gallide on a SiC substrate.

Abstract translation: 使用沉积在碳化硅半导体衬底上的镀镍和耐火硼化物来制造改进的半导体器件。 改变制造的沉积和退火参数可以提供具有更大阻挡高度和低理想性的更加热稳定的装置。 这种电性能的改进允许在高功率和高温应用中使用肖特基势垒二极管。 在一个实施方案中，将难熔金属硼化物层接合到碳化硅半导体衬底的表面。 难熔金属硼化物层在大于200℃的温度下沉积在硅碳半导体衬底上。在另一实施例中，通过在SiC衬底上沉积镍化镓来制造肖特基势垒二极管。

公开(公告)号：US20140213052A1

公开(公告)日：2014-07-31

申请号：US14188612

申请日：2014-02-24

Applicant: Teledyne Scientific & Imaging, LLC

Inventor： Miguel Urteaga ,  Richard L. Pierson, JR. ,  Keisuke Shinohara

IPC: H01L21/288 ,  H01L29/72 ,  H01L29/20

CPC classification number: H01L21/2885 ,  H01L21/76885 ,  H01L21/76897 ,  H01L29/20 ,  H01L29/66318 ,  H01L29/66462 ,  H01L29/72

Abstract: A system for forming self-aligned contacts includes electroplating a first metal contact onto a Group III-V semiconductor substrate, the first metal contact having a greater height than width and having a straight sidewall profile, etching back the semiconductor substrate down to a base layer to expose an emitter semiconductor layer under the first metal contact, conformally depositing a dielectric layer on a vertical side of the first metal contact, a vertical side of the emitter semiconductor layer and on the base layer, anisotropically etching the dielectric layer off of the semiconductor substrate to form a dielectric sidewall spacer on the vertical side of the first metal contact and providing a second metal contact immediately adjacent the dielectric sidewall spacer.

Abstract translation: 用于形成自对准触点的系统包括将第一金属触点电镀到III-V族半导体衬底上，第一金属触点具有比宽度更大的高度并且具有直的侧壁轮廓，将半导体衬底向后蚀刻到基底层 以在第一金属接触下露出发射极半导体层，在第一金属接触件的垂直侧，发射极半导体层的垂直侧和基极层上共形沉积电介质层，各向异性地将半导体上的电介质层蚀刻 衬底，以在第一金属触点的垂直侧上形成电介质侧壁间隔物，并提供紧邻电介质侧壁间隔物的第二金属触点。

公开(公告)号：US20120327608A1

公开(公告)日：2012-12-27

申请号：US13441598

申请日：2012-04-06

Applicant: John A. ROGERS ,  Matthew Meitl ,  Yugang Sun ,  Heung Cho Ko ,  Andrew Carlson ,  Won Mook Choi ,  Mark Stoykovich ,  Hanging Jiang ,  Yonggang Huang ,  Ralph G. Nuzzo ,  Zhengtao Zhu ,  Etienne Menard ,  Dahl-Young Khang

Inventor： John A. ROGERS ,  Matthew Meitl ,  Yugang Sun ,  Heung Cho Ko ,  Andrew Carlson ,  Won Mook Choi ,  Mark Stoykovich ,  Hanging Jiang ,  Yonggang Huang ,  Ralph G. Nuzzo ,  Zhengtao Zhu ,  Etienne Menard ,  Dahl-Young Khang

IPC: H05K7/06

CPC classification number: H01L29/72 ,  H01L21/02422 ,  H01L21/02628 ,  H01L21/4846 ,  H01L21/8258 ,  H01L23/5387 ,  H01L27/12 ,  H01L29/0657 ,  H01L2924/12041 ,  H01L2924/13091 ,  H05K1/0283 ,  H05K3/20 ,  H05K3/22 ,  H05K2201/0133 ,  H05K2201/09045 ,  H05K2203/0271 ,  H01L2924/00

Abstract: In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Abstract translation: 一方面，本发明提供了拉伸，压缩，弯曲或其它变形时能够提供良好性能的可拉伸和可选择的可印刷的部件，例如半导体和电子电路，以及制造或调谐这种可拉伸部件的相关方法。 对于一些应用而言，优选的可拉伸半导体和电子电路除了是可拉伸的之外是柔性的，因此能够沿着一个或多个轴显着地伸长，弯曲，弯曲或其它变形。 此外，本发明的可拉伸半导体和电子电路适用于宽范围的器件配置，以提供完全灵活的电子和光电器件。

公开(公告)号：US08039847B2

公开(公告)日：2011-10-18

申请号：US12844492

申请日：2010-07-27

Applicant: Ralph G. Nuzzo ,  John A. Rogers ,  Etienne Menard ,  Keon Jae Lee ,  Dahl-Young Khang ,  Yugang Sun ,  Matthew Meitl ,  Zhengtao Zhu ,  Heung Cho Ko ,  Shawn Mack

Inventor： Ralph G. Nuzzo ,  John A. Rogers ,  Etienne Menard ,  Keon Jae Lee ,  Dahl-Young Khang ,  Yugang Sun ,  Matthew Meitl ,  Zhengtao Zhu ,  Heung Cho Ko ,  Shawn Mack

IPC: H01L29/72 ,  H01L21/31 ,  B65C11/02 ,  C23F1/00

CPC classification number: H01L29/72 ,  B81C2201/0185 ,  B82Y10/00 ,  H01L21/02628 ,  H01L21/30 ,  H01L21/3083 ,  H01L21/31612 ,  H01L27/1285 ,  H01L27/1292 ,  H01L29/045 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1606 ,  H01L29/66265 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/78603 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696 ,  H01L31/0392 ,  H01L31/03925 ,  H01L31/03926 ,  H01L31/18 ,  H01L31/1804 ,  H01L2924/0002 ,  H01L2924/12041 ,  H01L2924/13091 ,  Y02E10/547 ,  Y02P70/521 ,  H01L2924/00

Abstract: The present invention provides a high yield pathway for the fabrication, transfer and assembly of high quality printable semiconductor elements having selected physical dimensions, shapes, compositions and spatial orientations. The compositions and methods of the present invention provide high precision registered transfer and integration of arrays of microsized and/or nanosized semiconductor structures onto substrates, including large area substrates and/or flexible substrates. In addition, the present invention provides methods of making printable semiconductor elements from low cost bulk materials, such as bulk silicon wafers, and smart-materials processing strategies that enable a versatile and commercially attractive printing-based fabrication platform for making a broad range of functional semiconductor devices.

Abstract translation: 本发明提供了用于制造，传输和组装具有选定的物理尺寸，形状，组成和空间取向的高质量可印刷半导体元件的高产率路径。 本发明的组合物和方法提供了高精度的记录转印和将微尺寸和/或纳米半导体结构的阵列集成到包括大面积衬底和/或柔性衬底的衬底上。 此外，本发明提供了从诸如散装硅晶片的低成本散装材料制造可印刷的半导体元件的方法，以及能够实现通用和商业上有吸引力的基于印刷的制造平台的智能材料处理策略，以制造广泛的功能性 半导体器件。

公开(公告)号：US5258625A

公开(公告)日：1993-11-02

申请号：US961547

申请日：1992-10-15

Applicant: Shiroo Kamohara ,  Toru Toyabe ,  Kozo Katayama ,  Shuichi Yamamoto ,  Sigeo Ihara

Inventor： Shiroo Kamohara ,  Toru Toyabe ,  Kozo Katayama ,  Shuichi Yamamoto ,  Sigeo Ihara

IPC: H01L21/82 ,  H01L21/8232 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/095 ,  H01L27/10 ,  H01L27/11 ,  H01L27/118 ,  H01L29/66 ,  H01L29/68 ,  H01L29/72 ,  H01L29/762 ,  H01L29/80 ,  H01L29/88 ,  H03K19/02

CPC classification number: B82Y10/00 ,  B82Y30/00 ,  H01L27/118 ,  H01L29/72 ,  H01L29/762 ,  H01L29/88 ,  H03K19/02 ,  Y10S977/937

Abstract: An interband single-electron tunnel transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.

Abstract translation: 带间单电子隧道晶体管利用通过p-n结的价带和导带之间的带间单电子隧道现象。 晶体管包括作为基本构成元件的微电容的组合，其通过将掺杂有杂质的p型半导体材料以费米能级与价带重叠的浓度与掺杂有杂质的n型半导体材料接合而形成 在费米能级与导带重叠的浓度下。 微容量包括具有结区的p-n结，由于库仑阻挡，带间电子隧道被阻止。

公开(公告)号：US4998155A

公开(公告)日：1991-03-05

申请号：US73305

申请日：1987-07-13

Applicant: Kikuo Watanabe ,  Tohru Nakamura ,  Toru Toyabe ,  Takahiro Okabe ,  Minoru Nagata

Inventor： Kikuo Watanabe ,  Tohru Nakamura ,  Toru Toyabe ,  Takahiro Okabe ,  Minoru Nagata

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/72 ,  H01L29/732

CPC classification number: H01L29/1008 ,  H01L29/1004 ,  H01L29/72 ,  Y10S257/906

Abstract: A radiation-hardened semiconductor device including a bipolar transistor is disclosed in which a highly-doped layer equal in conductivity type to and larger in impurity concentration than the base region of the transistor is formed in that portion of the surface of the base region which exists beneath an insulating film, to prevent minority carriers injected into the base region, from reaching the above-mentioned surface portion. Thus, the injected minority carriers can reach a collector region without being extinguished by the recombination at the surface of the base region.

Abstract translation: 公开了一种包括双极晶体管的辐射硬化半导体器件，其中在存在的基极区域的表面部分中形成了与晶体管的基极区相比导电类型等于或大于杂质浓度的高掺杂层 在绝缘膜下面，以防止注入基底区域的少数载流子到达上述表面部分。 因此，注入的少数载流子可以到达集电极区，而不会被基区表面的复合所熄灭。

公开(公告)号：US4969019A

公开(公告)日：1990-11-06

申请号：US90320

申请日：1987-08-27

Applicant: Sanjay K. Banerjee

Inventor： Sanjay K. Banerjee

IPC: H01L29/72 ,  H01L29/739

CPC classification number: H01L29/72 ,  H01L29/7391

Abstract: A semiconductor device for generating tunnel electron carries without a depleted PN junction. A heavily doped P-type semiconductor region (12) is formed in a lightly doped P-type semiconductor substrate (10), and spaced apart from a heavily doped N-type semiconductor region (18), forming a conduction channel (20) therebetween. A thin electrical insulator (14) is formed overlying the P-type region (12) and the conduction channel (20). A gate conductor (16) is formed overlying the thin insulating layer (14). Connections to the semiconductor device are provided by a substrate terminal (22) connected to the substrate (10), a gate terminal (24) connected to the gate conductor (16), and a drain terminal (26) connected to N-type semiconductor region (18). A voltage applied to the gate terminal (24) is effective to cause band bending in the P-type region (12) in excess of the band gap, thereby causing tunneling of electrons from the valence band to the conduction band. Inversion of the P-type region (12) is prevented by a drain voltage applied to the N-type region (18) which attracts conduction electrons.

Abstract translation: 用于产生隧道电子的半导体器件，没有耗尽的PN结。 在轻掺杂的P型半导体衬底（10）中形成重掺杂的P型半导体区（12），并与重掺杂的N型半导体区（18）隔开，在其间形成导通沟道（20） 。 形成了覆盖P型区域（12）和导电通道（20）的薄电绝缘体（14）。 形成覆盖在薄绝缘层（14）上的栅极导体（16）。 与半导体器件的连接由连接到基板（10）的基板端子（22），连接到栅极导体（16）的栅极端子（24）和连接到N型半导体的漏极端子 区域（18）。 施加到栅极端子（24）的电压有效地使P型区域（12）中的带宽弯曲超过带隙，从而导致电子从价带隧穿到导带。 通过施加到吸引导电电子的N型区域（18）的漏极电压来防止P型区域（12）的反转。