公开(公告)号：US07045412B2

公开(公告)日：2006-05-16

申请号：US10898257

申请日：2004-07-26

申请人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

发明人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

IPC分类号： H01L21/8238

CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/7835 ,  H03F3/601 ,  Y10S438/933

摘要： In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.

公开(公告)号：US20050003573A1

公开(公告)日：2005-01-06

申请号：US10898257

申请日：2004-07-26

申请人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

发明人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165 ,  H01L29/78 ,  H03F3/60 ,  H01L29/06

CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/7835 ,  H03F3/601 ,  Y10S438/933

摘要： In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.

摘要翻译： 在具有第一导电型和高杂质浓度的第一SiGe层的半导体多层结构中，形成具有第一导电型和低杂质浓度的第二SiGe层和具有低杂质浓度的Si层 在第一导电类型的Si衬底上依次另一个，在Si层的一部分中形成沟道，并且源极通过低杂质浓度的第二SiGe层，以电接触第一SiGe层的第一SiGe层 高杂质浓度或底物。

公开(公告)号：US06815707B2

公开(公告)日：2004-11-09

申请号：US10259396

申请日：2002-09-30

申请人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

发明人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

IPC分类号： H01L2904

CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/7835 ,  H03F3/601 ,  Y10S438/933

摘要： In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.

摘要翻译： 在具有第一导电型和高杂质浓度的第一SiGe层的半导体多层结构中，形成具有第一导电型和低杂质浓度的第二SiGe层和具有低杂质浓度的Si层 在第一导电类型的Si衬底上依次另一个，在Si层的一部分中形成沟道，并且源极通过低杂质浓度的第二SiGe层，以电接触第一SiGe层的第一SiGe层 高杂质浓度或底物。

公开(公告)号：US07095043B2

公开(公告)日：2006-08-22

申请号：US10790190

申请日：2004-03-02

申请人： Katsuya Oda ,  Nobuyuki Sugii ,  Makoto Miura ,  Isao Suzumura ,  Katsuyoshi Washio

发明人： Katsuya Oda ,  Nobuyuki Sugii ,  Makoto Miura ,  Isao Suzumura ,  Katsuyoshi Washio

IPC分类号： H01L29/06 ,  H01L31/0328

CPC分类号： H01L29/66068 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/1608

摘要： An (SiGe)C layer having a stoichiometric ratio of about 1:1 is locally formed on an Si layer, a large forbidden band width semiconductor device is prepared inside the layered structure thereof and an Si semiconductor integrated circuit is formed in the regions not formed with the layered structure, whereby high frequency high power operation of the device is enabled by the large forbidden band width semiconductor device and high performance is attained by hybridization of the Si integrated circuit.

摘要翻译： 在Si层上局部地形成化学计量比为约1:1的An（SiGe）C层，在其层叠结构内制备大的禁带宽半导体器件，并且在未形成的区域中形成Si半导体集成电路 具有分层结构，由此通过大的禁带宽半导体器件能够实现器件的高频高功率操作，并且通过Si集成电路的杂交获得高性能。

公开(公告)号：US06936875B2

公开(公告)日：2005-08-30

申请号：US10673789

申请日：2003-09-30

申请人： Nobuyuki Sugii ,  Kazuhiro Ohnishi ,  Katsuyoshi Washio

发明人： Nobuyuki Sugii ,  Kazuhiro Ohnishi ,  Katsuyoshi Washio

IPC分类号： H01L21/764 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/10 ,  H01L29/786 ,  H01L29/80

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78648 ,  H01L29/78687 ,  H01L29/802

摘要： With the invention, it is possible to avoid deterioration in short-channel characteristics, caused by a silicon germanium layer coming into contact with the channel of a strained SOI transistor. Further, it is possible to fabricate a double-gate type of strained SOI transistor or to implement mixedly mounting the strained SOI transistor and a conventional silicon or SOI transistor on the same wafer. According to the invention, for example, a strained silicon layer is grown on a strain-relaxed silicon germanium layer, and subsequently, portions of the silicon germanium layer are removed, thereby constituting a channel layer in the strained silicon layer.

摘要翻译： 利用本发明，可以避免由与应变SOI晶体管的沟道接触的硅锗层引起的短沟道特性的劣化。 此外，可以制造双栅型应变SOI晶体管，或者在同一晶片上实现将应变SOI晶体管和常规硅或SOI晶体管混合安装。 根据本发明，例如，在应变松弛硅锗层上生长应变硅层，随后去除硅锗层的部分，从而在应变硅层中构成沟道层。

公开(公告)号：US06723541B2

公开(公告)日：2004-04-20

申请号：US10163312

申请日：2002-06-07

申请人： Nobuyuki Sugii ,  Shinya Yamaguchi ,  Katsuyoshi Washio

发明人： Nobuyuki Sugii ,  Shinya Yamaguchi ,  Katsuyoshi Washio

IPC分类号： H01L2100

CPC分类号： H01L21/3247 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/02667 ,  H01L21/3226 ,  H01L21/76251 ,  H01L21/84 ,  H01L27/1203 ,  Y10S438/933

摘要： A method of producing a strain-relaxed Si—Ge virtual substrate for use in a semiconductor substrate which is planar and of less defects for improving the performance of a field effect semiconductor device, which method comprises covering an Si—Ge layer formed on an SOI substrate with an insulating layer to prevent evaporation of Ge, heating the mixed layer of silicon and germanium at a temperature higher than a solidus curve temperature determined by the germanium content of the Si—Ge layer into a partially melting state, and diffusing germanium to the Si layer on the insulating layer, thereby solidifying the molten Si—Ge layer to obtain a strain-relaxed Si—Ge virtual substrate.

摘要翻译： 一种制造用于半导体衬底的应变松弛Si-Ge虚拟衬底的方法，该半导体衬底是平面的，并且具有较少的缺陷，用于提高场效应半导体器件的性能，该方法包括覆盖形成在SOI上的Si-Ge层 具有绝缘层的衬底以防止Ge的蒸发，在高于由Si-Ge层的锗含量确定的固相线曲线温度的部分熔融状态下加热硅和锗的混合层，并将锗扩散到 Si层，从而使熔融的Si-Ge层固化，得到应变松弛的Si-Ge虚拟基板。

公开(公告)号：US08212615B2

公开(公告)日：2012-07-03

申请号：US12765010

申请日：2010-04-22

申请人： Toru Masuda ,  Nobuhiro Shiramizu ,  Takahiro Nakamura ,  Katsuyoshi Washio

发明人： Toru Masuda ,  Nobuhiro Shiramizu ,  Takahiro Nakamura ,  Katsuyoshi Washio

IPC分类号： H03F3/45 ,  H03F3/191

CPC分类号： H03G3/3052

摘要： There is disclosed a variable-gain amplifier circuit that operates on a low voltage, exhibits low distortion, provides a wide range of variation, and is suitable for use in a low-power-consumption wireless communication system. The variable-gain amplifier circuit is configured so that a variable-load circuit, which includes three reactance function elements and provides a wide range of impedance variation, is connected to a conductor circuit whose output terminal generates a positive-phase output current proportional to conductance with respect to an input voltage.

摘要翻译： 公开了一种在低电压下操作的可变增益放大器电路，具有低失真，提供宽范围的变化，并且适用于低功耗无线通信系统。 可变增益放大器电路被配置为使得包括三个电抗功能元件并提供宽范围的阻抗变化的可变负载电路连接到其输出端产生与电导成比例的正相输出电流的导体电路 相对于输入电压。

公开(公告)号：US07098740B2

公开(公告)日：2006-08-29

申请号：US10688976

申请日：2003-10-21

申请人： Masao Kondo ,  Toru Masuda ,  Katsuyoshi Washio

发明人： Masao Kondo ,  Toru Masuda ,  Katsuyoshi Washio

IPC分类号： H03F3/68

CPC分类号： H03F3/211 ,  H03F1/302 ,  H03F2200/372 ,  H03F2203/21178

摘要： There is provided not only a radio frequency power amplifier using an SiGe HBT subject to a little amplification distortion, but also a communication system using the same. A conventional radio frequency power amplifier provides base bias paths of transistors Q1 through QN (SiGe HBT) with bias resistors R11 through R1N having resistance values three to five times higher than those of a ballast resistor attached to each transistor's base. A coil LB is provided in parallel with the bias resistor as a means for compensating a voltage drop due to direct current component IDC flowing through the bias resistor. Addition of the bias resistor suppresses non-linearity of low-frequency variations in an output current. Addition of the coil compensates for voltage drop. Accordingly, the maximum linear output power can be improved. As a result, it is possible to provide the power amplifier subject to a little amplification distortion within a wide output range.

摘要翻译： 不仅提供使用SiGe HBT的射频功率放大器，而且具有很小的放大失真，而且还提供了使用它的通信系统。 传统的射频功率放大器提供具有偏置电阻器R11至R11的晶体管Q 1至Q N（SiGe HBT）的基极偏置路径， SUB> 1N 的电阻值是连接到每个晶体管基极的镇流电阻的三到五倍。 作为用于补偿流过偏置电阻器的直流分量I DC的电压降的装置，设置有与偏压电阻并联的线圈L B B。 增加偏置电阻抑制输出电流中低频变化的非线性。 线圈的添加补偿电压降。 因此，可以提高最大线性输出功率。 结果，可以在宽的输出范围内提供具有小的放大失真的功率放大器。

公开(公告)号：US20050001238A1

公开(公告)日：2005-01-06

申请号：US10855378

申请日：2004-05-28

申请人： Eiji Oue ,  Katsuyoshi Washio ,  Hiromi Shimamoto ,  Katsuya Oda ,  Makoto Miura

发明人： Eiji Oue ,  Katsuyoshi Washio ,  Hiromi Shimamoto ,  Katsuya Oda ,  Makoto Miura

IPC分类号： H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L31/0328

CPC分类号： H01L29/66287 ,  H01L29/7322

摘要： A bipolar transistor is provided in which both the base resistance and the base-collector capacitance are reduced and which is capable of operating at a high cutoff frequency. The semiconductor device is structured so that the emitter and extrinsic base are separated from each other by an insulator sidewall and the bottom faces of the insulator sidewall, and the emitter are approximately on the same plane. The extrinsic base electrode and the collector region are separated from each other by an insulator.

摘要翻译： 提供双极晶体管，其中基极电阻和基极集电极电容都减小，并且能够以高截止频率工作。 半导体器件被构造成使得发射极和非本征基极通过绝缘体侧壁和绝缘体侧壁的底面彼此分离，并且发射极大致在同一平面上。 外部基极和集电极区域通过绝缘体彼此分离。

公开(公告)号：US06667489B2

公开(公告)日：2003-12-23

申请号：US10299837

申请日：2002-11-20

申请人： Isao Suzumura ,  Katsuya Oda ,  Katsuyoshi Washio

发明人： Isao Suzumura ,  Katsuya Oda ,  Katsuyoshi Washio

IPC分类号： H01L2906

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A high-speed heterojunction bipolar transistor in a large injection of electrons from the emitter and a method for production thereof. In a typical example of the SiGeC heterojunction bipolar transistor, the collector has a layer of n-type single-crystal Si and a layer of n-type single-crystal SiGe, the base is a layer of heavily doped p-type single-crystal SiGeC, and the emitter is a layer of n-type single-crystal Si. At the heterointerface between the layer of n-type single-crystal SiGe and the layer of p-type single-crystal SiGeC, the bandgap of the p-type single-crystal SiGeC is larger than that of the layer of n-type single-crystal SiGe. Even though the effective neutral base expands due to an increase in electrons injected from the emitter, no energy barrier occurs in the conduction band at the heterointerface between the layer of n-type single-crystal SiGe and the layer of p-type single-crystal SiGeC. Thus, the diffusion of electrons is not inhibited and it is possible to realize high-speed heterojunction bipolar transistors even in the high injection state.

摘要翻译： 从发射极大量注入电子的高速异质结双极晶体管及其制造方法。 在SiGeC异质结双极晶体管的典型实例中，集电体具有n型单晶Si层和n型单晶SiGe层，基极是重掺杂p型单晶层 SiGeC，发射极是n型单晶Si层。 在n型单晶SiGe层和p型单晶SiGeC层之间的异质界面处，p型单晶SiGeC的带隙大于n型单晶SiGeC层的带隙， 水晶SiGe。 即使有效的中性碱基由于从发射体注入的电子的增加而扩大，在n型单晶SiGe层与p型单晶层之间的异质界面的导带中也不发生能量势垒 SiGeC。 因此，电子的扩散不被抑制，即使在高注入状态下也可以实现高速异质结双极晶体管。