公开(公告)号：US07045412B2

公开(公告)日：2006-05-16

申请号：US10898257

申请日：2004-07-26

申请人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

发明人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

IPC分类号： H01L21/8238

CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/7835 ,  H03F3/601 ,  Y10S438/933

摘要： In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.

公开(公告)号：US20050003573A1

公开(公告)日：2005-01-06

申请号：US10898257

申请日：2004-07-26

申请人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

发明人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165 ,  H01L29/78 ,  H03F3/60 ,  H01L29/06

CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/7835 ,  H03F3/601 ,  Y10S438/933

摘要： In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.

摘要翻译： 在具有第一导电型和高杂质浓度的第一SiGe层的半导体多层结构中，形成具有第一导电型和低杂质浓度的第二SiGe层和具有低杂质浓度的Si层 在第一导电类型的Si衬底上依次另一个，在Si层的一部分中形成沟道，并且源极通过低杂质浓度的第二SiGe层，以电接触第一SiGe层的第一SiGe层 高杂质浓度或底物。

公开(公告)号：US06815707B2

公开(公告)日：2004-11-09

申请号：US10259396

申请日：2002-09-30

申请人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

发明人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

IPC分类号： H01L2904

CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/7835 ,  H03F3/601 ,  Y10S438/933

摘要： In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.

摘要翻译： 在具有第一导电型和高杂质浓度的第一SiGe层的半导体多层结构中，形成具有第一导电型和低杂质浓度的第二SiGe层和具有低杂质浓度的Si层 在第一导电类型的Si衬底上依次另一个，在Si层的一部分中形成沟道，并且源极通过低杂质浓度的第二SiGe层，以电接触第一SiGe层的第一SiGe层 高杂质浓度或底物。

公开(公告)号：US06723541B2

公开(公告)日：2004-04-20

申请号：US10163312

申请日：2002-06-07

申请人： Nobuyuki Sugii ,  Shinya Yamaguchi ,  Katsuyoshi Washio

发明人： Nobuyuki Sugii ,  Shinya Yamaguchi ,  Katsuyoshi Washio

IPC分类号： H01L2100

CPC分类号： H01L21/3247 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/02667 ,  H01L21/3226 ,  H01L21/76251 ,  H01L21/84 ,  H01L27/1203 ,  Y10S438/933

摘要： A method of producing a strain-relaxed Si—Ge virtual substrate for use in a semiconductor substrate which is planar and of less defects for improving the performance of a field effect semiconductor device, which method comprises covering an Si—Ge layer formed on an SOI substrate with an insulating layer to prevent evaporation of Ge, heating the mixed layer of silicon and germanium at a temperature higher than a solidus curve temperature determined by the germanium content of the Si—Ge layer into a partially melting state, and diffusing germanium to the Si layer on the insulating layer, thereby solidifying the molten Si—Ge layer to obtain a strain-relaxed Si—Ge virtual substrate.

摘要翻译： 一种制造用于半导体衬底的应变松弛Si-Ge虚拟衬底的方法，该半导体衬底是平面的，并且具有较少的缺陷，用于提高场效应半导体器件的性能，该方法包括覆盖形成在SOI上的Si-Ge层 具有绝缘层的衬底以防止Ge的蒸发，在高于由Si-Ge层的锗含量确定的固相线曲线温度的部分熔融状态下加热硅和锗的混合层，并将锗扩散到 Si层，从而使熔融的Si-Ge层固化，得到应变松弛的Si-Ge虚拟基板。

公开(公告)号：US07095043B2

公开(公告)日：2006-08-22

申请号：US10790190

申请日：2004-03-02

申请人： Katsuya Oda ,  Nobuyuki Sugii ,  Makoto Miura ,  Isao Suzumura ,  Katsuyoshi Washio

发明人： Katsuya Oda ,  Nobuyuki Sugii ,  Makoto Miura ,  Isao Suzumura ,  Katsuyoshi Washio

IPC分类号： H01L29/06 ,  H01L31/0328

CPC分类号： H01L29/66068 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/1608

摘要： An (SiGe)C layer having a stoichiometric ratio of about 1:1 is locally formed on an Si layer, a large forbidden band width semiconductor device is prepared inside the layered structure thereof and an Si semiconductor integrated circuit is formed in the regions not formed with the layered structure, whereby high frequency high power operation of the device is enabled by the large forbidden band width semiconductor device and high performance is attained by hybridization of the Si integrated circuit.

摘要翻译： 在Si层上局部地形成化学计量比为约1:1的An（SiGe）C层，在其层叠结构内制备大的禁带宽半导体器件，并且在未形成的区域中形成Si半导体集成电路 具有分层结构，由此通过大的禁带宽半导体器件能够实现器件的高频高功率操作，并且通过Si集成电路的杂交获得高性能。

公开(公告)号：US06936875B2

公开(公告)日：2005-08-30

申请号：US10673789

申请日：2003-09-30

申请人： Nobuyuki Sugii ,  Kazuhiro Ohnishi ,  Katsuyoshi Washio

发明人： Nobuyuki Sugii ,  Kazuhiro Ohnishi ,  Katsuyoshi Washio

IPC分类号： H01L21/764 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/10 ,  H01L29/786 ,  H01L29/80

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78648 ,  H01L29/78687 ,  H01L29/802

摘要： With the invention, it is possible to avoid deterioration in short-channel characteristics, caused by a silicon germanium layer coming into contact with the channel of a strained SOI transistor. Further, it is possible to fabricate a double-gate type of strained SOI transistor or to implement mixedly mounting the strained SOI transistor and a conventional silicon or SOI transistor on the same wafer. According to the invention, for example, a strained silicon layer is grown on a strain-relaxed silicon germanium layer, and subsequently, portions of the silicon germanium layer are removed, thereby constituting a channel layer in the strained silicon layer.

摘要翻译： 利用本发明，可以避免由与应变SOI晶体管的沟道接触的硅锗层引起的短沟道特性的劣化。 此外，可以制造双栅型应变SOI晶体管，或者在同一晶片上实现将应变SOI晶体管和常规硅或SOI晶体管混合安装。 根据本发明，例如，在应变松弛硅锗层上生长应变硅层，随后去除硅锗层的部分，从而在应变硅层中构成沟道层。

公开(公告)号：US08183635B2

公开(公告)日：2012-05-22

申请号：US12756451

申请日：2010-04-08

申请人： Nobuyuki Sugii ,  Ryuta Tsuchiya ,  Shinichiro Kimura ,  Takashi Ishigaki ,  Yusuke Morita ,  Hiroyuki Yoshimoto

发明人： Nobuyuki Sugii ,  Ryuta Tsuchiya ,  Shinichiro Kimura ,  Takashi Ishigaki ,  Yusuke Morita ,  Hiroyuki Yoshimoto

IPC分类号： H01L21/00

CPC分类号： H01L27/1203 ,  H01L21/76283

摘要： A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.

摘要翻译： 通过改善在SOI衬底的浅沟槽和SOI层的边界部分的形状来实现低功耗的半导体器件的技术。 硅衬底的主表面和沿着SOI层的侧表面延伸的线交叉的位置（SOI边缘）比浅沟槽隔离更远离位于（STI边缘）的位置（STI边缘），在该位置处 沿着浅沟槽的侧壁延伸并且沿着硅衬底的主表面延伸的线交叉，并且在STI边缘处的硅衬底的拐角具有弯曲表面。

公开(公告)号：US20100258871A1

公开(公告)日：2010-10-14

申请号：US12759559

申请日：2010-04-13

申请人： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii

发明人： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： Characteristics of a semiconductor device having a FINFET are improved. The FINFET has: a channel layer arranged in an arch shape on a semiconductor substrate and formed of monocrystalline silicon; a front gate electrode formed on a part of an outside of the channel layer through a front gate insulating film; and a back gate electrode formed so as to be buried inside the channel layer through a back gate insulating film. The back gate electrode arranged inside the arch shape is arranged so as to pass through the front gate electrode.

摘要翻译： 具有FINFET的半导体器件的特性得到改善。 FINFET具有：在半导体衬底上以拱形形式布置并由单晶硅形成的沟道层; 前栅电极，其通过前栅极绝缘膜形成在沟道层的外部的一部分上; 以及形成为通过背栅绝缘膜埋设在沟道层内的背栅电极。 布置在拱形内侧的背栅极布置成穿过前栅电极。

公开(公告)号：US20080203403A1

公开(公告)日：2008-08-28

申请号：US11960680

申请日：2007-12-19

申请人： Takayuki Kawahara ,  Masanao Yamaoka ,  Nobuyuki Sugii

发明人： Takayuki Kawahara ,  Masanao Yamaoka ,  Nobuyuki Sugii

IPC分类号： H01L33/00 ,  H01L27/12

CPC分类号： H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/1203 ,  H01L27/153

摘要： The semiconductor integrated circuit (1) has a memory (4) and a logic circuit (5), which are mixedly palletized on a silicon substrate (2). The memory includes a partially-depleted type nMOS (6) having an SOI structure and formed on UTB (3). The partially-depleted type nMOS has a backgate region (14) under UTB, to which a voltage can be applied independently of a corresponding gate terminal. The logic circuit includes an nMOS (7) and a pMOS (8), and both are of a fully-depleted type, formed on UTB and have an SOI structure. The fully-depleted type nMOS and pMOS have backgate regions (14, 22) under respective UTBs, to which voltages can be applied independently of the corresponding gate terminals

摘要翻译： 半导体集成电路（1）具有在硅衬底（2）上混合堆垛的存储器（4）和逻辑电路（5）。 存储器包括具有SOI结构并形成在UTB（3）上的部分耗尽型nMOS（6）。 部分耗尽型nMOS在UTB之下具有背栅区域（14），独立于对应的栅极端子可以施加电压。 逻辑电路包括nMOS（7）和pMOS（8），并且它们都是完全耗尽型的，形成在UTB上并具有SOI结构。 完全耗尽型nMOS和pMOS在相应的UTB下具有背栅区域（14,22），可以独立于对应的栅极端子施加电压

公开(公告)号：US20080111134A1

公开(公告)日：2008-05-15

申请号：US11969488

申请日：2008-01-04

申请人： Shinya Yamaguchi ,  Masanobu Miyao ,  Nobuyuki Sugii ,  Seang-kee Park ,  Kiyokazu Nakagawa

发明人： Shinya Yamaguchi ,  Masanobu Miyao ,  Nobuyuki Sugii ,  Seang-kee Park ,  Kiyokazu Nakagawa

IPC分类号： H01L29/10 ,  H01L21/00

CPC分类号： H01L29/78696 ,  G09G3/3648 ,  G09G2300/0408 ,  H01L27/1277 ,  H01L27/1281 ,  H01L27/1296 ,  H01L29/04 ,  H01L29/045 ,  H01L29/41733 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/78666 ,  H01L29/78669 ,  H01L29/78675 ,  H01L29/78678

摘要： To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.

摘要翻译： 为了提供具有较高电子迁移率的改进的低温多晶层的TFT，并且鉴于通过利用玻璃基板实现具有大的显示面积的液晶显示装置，确保制造中的波动较小。 通过利用与金刚石结构的{111}双边界结合的多晶晶粒形成的半导体薄膜（称为准单晶薄膜），可以在特定波动的预定范围内实现具有较高电子迁移率的TFT 作为TFT的沟道区域（即有源区）。