公开(公告)号：US06815707B2

公开(公告)日：2004-11-09

申请号：US10259396

申请日：2002-09-30

申请人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

发明人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

IPC分类号： H01L2904

CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/7835 ,  H03F3/601 ,  Y10S438/933

摘要： In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.

摘要翻译： 在具有第一导电型和高杂质浓度的第一SiGe层的半导体多层结构中，形成具有第一导电型和低杂质浓度的第二SiGe层和具有低杂质浓度的Si层 在第一导电类型的Si衬底上依次另一个，在Si层的一部分中形成沟道，并且源极通过低杂质浓度的第二SiGe层，以电接触第一SiGe层的第一SiGe层 高杂质浓度或底物。

公开(公告)号：US07045412B2

公开(公告)日：2006-05-16

申请号：US10898257

申请日：2004-07-26

申请人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

发明人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

IPC分类号： H01L21/8238

CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/7835 ,  H03F3/601 ,  Y10S438/933

摘要： In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.

公开(公告)号：US20050003573A1

公开(公告)日：2005-01-06

申请号：US10898257

申请日：2004-07-26

申请人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

发明人： Nobuyuki Sugii ,  Masatoshi Morikawa ,  Isao Yoshida ,  Katsuyoshi Washio

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165 ,  H01L29/78 ,  H03F3/60 ,  H01L29/06

CPC分类号： H01L29/66659 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/7835 ,  H03F3/601 ,  Y10S438/933

摘要： In a semiconductor multi-layer structure in which a first SiGe layer having a first conductivity-type and high impurity concentration, a second SiGe layer having the first conductivity-type and a low impurity concentration and a Si layer having a low impurity concentration are formed one on another in this order on a Si substrate of the first conductivity-type, a channel is formed in a part of the Si layer and a source electrode passes through the second SiGe layer of low impurity concentration to electrically contact the first SiGe layer of high impurity concentration or the substrate.

摘要翻译： 在具有第一导电型和高杂质浓度的第一SiGe层的半导体多层结构中，形成具有第一导电型和低杂质浓度的第二SiGe层和具有低杂质浓度的Si层 在第一导电类型的Si衬底上依次另一个，在Si层的一部分中形成沟道，并且源极通过低杂质浓度的第二SiGe层，以电接触第一SiGe层的第一SiGe层 高杂质浓度或底物。

公开(公告)号：US06492872B1

公开(公告)日：2002-12-10

申请号：US09657237

申请日：2000-09-07

申请人： Toru Fujioka ,  Yoshikuni Matsunaga ,  Isao Yoshida ,  Masatoshi Morikawa ,  Masao Hotta ,  Tetsuaki Adachi

发明人： Toru Fujioka ,  Yoshikuni Matsunaga ,  Isao Yoshida ,  Masatoshi Morikawa ,  Masao Hotta ,  Tetsuaki Adachi

IPC分类号： H03G310

CPC分类号： H03F1/301 ,  H03G3/3042

摘要： A high frequency power amplifier module is provided for improving output controllability. A wireless communication apparatus incorporates a high frequency power amplifier module in a multi-stage configuration including a plurality of cascaded MOSFETS. The power amplifier module comprises a bias circuit for generating a gate voltage in response to a power control voltage (vapc) generated based on a power control signal of the wireless communication apparatus. The gate voltage has a bias pattern which presents smaller fluctuations in output power in response to a control voltage (Vapc) in a region near a threshold voltage (Vth) of the MOSFETs in respective amplification stages. In this way, the controllability for the output power is improved. More specifically, the power amplifier module has a gate bias circuit for generating the gate voltage (Vg) which follows a gate voltage pattern. The gate voltage (Vg) supplied to a control terminal in response to the control voltage (Vapc) largely changes in a region where the gate voltage (Vg) is lower than the threshold voltage (Vth) of the respective MOSFETs, and slightly changes near the threshold voltage (Vth). Also, the gate voltage (Vg) presents desired characteristics from the vicinity of the threshold voltage (Vth) to a high Vapc voltage region.

摘要翻译： 提供了一种用于提高输出可控性的高频功率放大器模块。 无线通信装置将包括多个级联MOSFET的多级配置的高频功率放大器模块结合在一起。 功率放大器模块包括用于响应于基于无线通信设备的功率控制信号产生的功率控制电压（vapc）产生栅极电压的偏置电路。 栅极电压具有偏置图案，其响应于在各个放大级中的MOSFET的阈值电压（Vth）附近的区域中的控制电压（Vapc），输出功率的波动较小。 以这种方式，提高了输出功率的可控性。 更具体地，功率放大器模块具有用于产生跟随栅极电压图案的栅极电压（Vg）的栅极偏置电路。 响应于控制电压（Vapc）而提供给控制端的栅极电压（Vg）在栅极电压（Vg）低于各个MOSFET的阈值电压（Vth）的区域内大大变化，并且稍微改变 阈值电压（Vth）。 此外，栅极电压（Vg）从阈值电压（Vth）附近到高Vapc电压区域呈现期望的特性。

公开(公告)号：US20110220999A1

公开(公告)日：2011-09-15

申请号：US13111001

申请日：2011-05-19

申请人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

发明人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

IPC分类号： H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/4827 ,  H01L23/53219 ,  H01L23/53295 ,  H01L27/0255 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/7835 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).

摘要翻译： 在具有漏极偏移区域的高频放大MOSFET中，通过在源极区域10，漏极区域9和浸出层9上引出电极的导体插头13（P1）来减小尺寸并降低导通电阻。 连接有第一层布线11a，11d（M1）的第3层（4），另外，背面的第二层布线12a〜12d在导体插塞13（P1）上连接到第一层布线11s，11d（M1 ）。

公开(公告)号：US5379230A

公开(公告)日：1995-01-03

申请号：US232402

申请日：1994-04-25

申请人： Masatoshi Morikawa ,  Isao Yoshida ,  Terumi Sawase ,  Kouzou Sakamoto ,  Takeaki Okabe

发明人： Masatoshi Morikawa ,  Isao Yoshida ,  Terumi Sawase ,  Kouzou Sakamoto ,  Takeaki Okabe

IPC分类号： G06F1/00 ,  G01Q70/00 ,  G05F1/56 ,  H01L21/822 ,  H01L27/04 ,  H03K17/08 ,  H03K17/082 ,  H03M1/08 ,  G01K7/00 ,  H03K17/12

CPC分类号： H03K17/18 ,  H03K17/0822 ,  H03K2017/0806

摘要： A semiconductor integrated circuit has a semiconductor output device (3) , a sensor (5) generating an electric signal (7) relevant to heat generation (6) of the output device (3) and a microprocessor unit MPU 2, inside a chip (1). The MPU (2) is constructed of a memory (20) and CPU (22). The electric signal (7) generated from the sensor (5) is processed by the CPU (22) in accordance with a stored program of the memory (20). Accordingly, the drivability of the semiconductor output device (3) can be set in an optimum state corresponding to changes in chip temperature including changes that are only momentary.

摘要翻译： 半导体集成电路具有半导体输出装置（3），产生与输出装置（3）的发热（6）有关的电信号（7）的传感器（5）和芯片内的微处理器单元MPU2 1）。 MPU（2）由存储器（20）和CPU（22）构成。 根据存储器（20）的存储程序，由CPU（22）处理从传感器（5）产生的电信号（7）。 因此，可以将半导体输出装置（3）的驾驶性能设定为对应于仅包含瞬时变化的芯片温度变化的最佳状态。

公开(公告)号：US20100044793A1

公开(公告)日：2010-02-25

申请号：US12609323

申请日：2009-10-30

申请人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

发明人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

IPC分类号： H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/4827 ,  H01L23/53219 ,  H01L23/53295 ,  H01L27/0255 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/7835 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d(M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).

摘要翻译： 在具有漏极偏移区域的高频放大MOSFET中，通过在源极区域10，漏极区域9和浸出层9上引出电极的导体插头13（P1）来减小尺寸并降低导通电阻。 连接有第一层布线11a，11d（M1）的第3层（4），另外，背面的第二层布线12a〜12d在导体插塞13（P1）上连接到第一层布线11s，11d（M1 ）。

公开(公告)号：US20050173738A1

公开(公告)日：2005-08-11

申请号：US11049998

申请日：2005-02-04

申请人： Masao Kondo ,  Yutaka Hoshino ,  Kazuhiro Ohnishi ,  Isao Yoshida ,  Masatoshi Morikawa

发明人： Masao Kondo ,  Yutaka Hoshino ,  Kazuhiro Ohnishi ,  Isao Yoshida ,  Masatoshi Morikawa

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/45 ,  H01L29/80

CPC分类号： H01L29/66659 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0886 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/456 ,  H01L29/66628 ,  H01L29/7835 ,  H01L29/7842

摘要： Provided is a technology capable of reducing the on-resistance of a power MISFET while suppressing the generation of defects in a strained silicon layer. A strained silicon layer is formed only over an underlying strained silicon layer in the drain region by epitaxial growth. Large portions of a lightly-doped n type impurity diffusion region, offset region and heavily-doped n type impurity diffusion region are formed in these strained silicon layers, having a higher electron mobility than a conventional silicon layer.

摘要翻译： 提供了一种能够在抑制应变硅层中的缺陷的产生的同时降低功率MISFET的导通电阻的技术。 通过外延生长仅在漏极区域中的下层应变硅层上形成应变硅层。 在这些应变硅层中形成大量的轻掺杂n型杂质扩散区域，偏移区域和重掺杂n型杂质扩散区域，其具有比常规硅层更高的电子迁移率。

公开(公告)号：US20050017296A1

公开(公告)日：2005-01-27

申请号：US10921327

申请日：2004-08-19

申请人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

发明人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L23/482 ,  H01L23/532 ,  H01L27/04 ,  H01L27/088 ,  H01L29/417 ,  H01L29/80

CPC分类号： H01L29/66659 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/4827 ,  H01L23/53219 ,  H01L23/53295 ,  H01L27/0255 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/7835 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).

摘要翻译： 在具有漏极偏移区域的高频放大MOSFET中，通过在源极区域10，漏极区域9和浸出层9上引出电极的导体插头13（P1）来减小尺寸并降低导通电阻。 连接有第一层布线11a，11d（M1）的第3层（4），另外，背面的第二层布线12a〜12d在导体插塞13（P1）上连接到第一层布线11s，11d（M1 ）。

公开(公告)号：US5638246A

公开(公告)日：1997-06-10

申请号：US10572

申请日：1993-01-28

申请人： Kozo Sakamoto ,  Isao Yoshida ,  Masatoshi Morikawa ,  Shigeo Ohtaka ,  Hideki Tsunoda

发明人： Kozo Sakamoto ,  Isao Yoshida ,  Masatoshi Morikawa ,  Shigeo Ohtaka ,  Hideki Tsunoda

IPC分类号： H02H5/04 ,  H03K17/08 ,  H03K17/082

CPC分类号： H02H5/044 ,  H03K17/0822 ,  H03K2017/0806

摘要： In a semiconductor device including a power MOSFET (M.sub.0) for the output stage, a temperature detection circuit produces an output signal upon detecting an abnormal rise in the chip temperature, the signal turns on a set input element (M.sub.1) in a latch circuit so that the latch circuit becomes a set state, the set output of the latch circuit turns on a control element (M.sub.5), causing the power MOSFET to become non-conductive so that it is protected from destruction. The latch circuit is not brought to a reset state even if the external gate terminal of the device is brought to zero volt. With a voltage outside the range of the normal input signal, e.g., a large negative voltage, being applied to the external gate terminal, the gate capacitance of the control element (M.sub.5) discharges, and consequently the latch circuit is brought to the reset state and the protective operation is cancelled. The semiconductor device is further provided with an external reset terminal, and the protective operation can also be cancelled through the application of a reset signal to the external reset terminal. The semiconductor device is protected from destruction and also from deterioration of characteristics of the power MOSFET (M.sub.0), and yet the protective operation is not cancelled erroneously by the normal input signal.

摘要翻译： 在包括用于输出级的功率MOSFET（M0）的半导体器件中，温度检测电路在检测到芯片温度的异常升高时产生输出信号，该信号使锁存电路中的设定输入元件（M1）接通，从而 锁存电路变为置位状态，锁存电路的设定输出导通控制元件（M5），使功率MOSFET变得不导通，从而防止其破坏。 即使器件的外部栅极端子达到零伏，锁存电路也不会进入复位状态。 在外部栅极端子施加正常输入信号（例如，大的负电压）的范围之外的电压时，控制元件（M5）的栅极电容放电，因此锁存电路进入复位状态 并且保护操作被取消。 半导体器件还具有外部复位端子，并且还可以通过向外部复位端子施加复位信号来取消保护操作。 保护半导体器件不受破坏，也可以防止功率MOSFET（M0）的特性恶化，而保护操作也不会被正常输入信号错误地消除。