公开(公告)号：US6090684A

公开(公告)日：2000-07-18

申请号：US363184

申请日：1999-07-29

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Masayuki Kojima ,  Kota Funayama

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Masayuki Kojima ,  Kota Funayama

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L29/78

CPC分类号： H01L21/76232 ,  Y10S148/05

摘要： A shallow groove isolation structure (SGI) electrically insulates adjoining transistors on a semiconductor substrate. A pad oxide film is formed on the semiconductor substrate and an oxidation inhibition film is formed on the pad oxide film. Parts of the oxide inhibition film and pad oxide film are removed to form the groove. In particular, the pad oxide film is removed from an upper edge of the groove within a range of 5 to 40 nm. A region of the groove is oxidized in an oxidation environment with a cast ratio of hydrogen (H.sub.2) to oxygen (O.sub.2) being less than or equal to 0.5. At this ratio, the oxidizing progresses under low stress at the upper groove edges of the substrate thereby enabling rounding of the upper groove edges without creating a level difference at or near the upper groove edge on the substrate surface.

摘要翻译： 浅沟隔离结构（SGI）使半导体衬底上的相邻晶体管电绝缘。 在半导体基板上形成衬垫氧化膜，在衬垫氧化膜上形成氧化抑制膜。 除去氧化物抑制膜和垫氧化膜的一部分以形成槽。 特别地，在5〜40nm的范围内，从槽的上边缘去除衬垫氧化膜。 凹槽的区域在氢（H 2）与氧（O 2）的铸造比小于或等于0.5的氧化环境中被氧化。 在该比例下，在基板的上槽边缘处的低应力下氧化进行，从而能够在上槽边缘的四舍五入，而不会在基板表面上的上槽边缘处或附近产生水平差。

公开(公告)号：US06403446B1

公开(公告)日：2002-06-11

申请号：US09536447

申请日：2000-03-28

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Masayuki Kojima ,  Kota Funayama

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Masayuki Kojima ,  Kota Funayama

IPC分类号： H01L2176

CPC分类号： H01L21/76232 ,  Y10S148/05

摘要： Manufacturing a semiconductor device avoiding an increase of transistor leak current or reduction of the withstanding voltage characteristics is by at least one of: The pad oxide film is removed along the substrate surface from the upper edge of the groove over a distance ranging from 5 to 40 nm: The exposed surface of the semiconductor substrate undergoes removal by isotropic etching within 20 nm; and oxidizing a groove portion formed in a semiconductor substrate in an oxidation environment with a gas ratio of hydrogen (H2) to oxygen (O2) being less than or equal to 0.5, an increase of the curvature radius beyond 3nm is achieved without associating the risk of creation of any level difference on the substrate surface at or near the upper groove edge portions in a groove separation structure. This eliminates either an increase of transistor leak current or reduction of the withstanding voltage characteristics thereof otherwise occurring due to local electric field concentration near or around the terminate ends of a gate electrode film which in turn leads to an ability to improve electrical reliability of transistors used.

摘要翻译： 制造半导体器件避免晶体管泄漏电流的增加或耐压特性的降低是至少以下之一：衬垫氧化膜沿着衬底表面从沟槽的上边缘移除5至40的距离 nm：通过各向同性蚀刻在20nm内去除半导体衬底的暴露表面; 并且在氧（H2）与氧气（O2）的气体比小于或等于0.5的氧化环境中氧化形成在半导体衬底中的沟槽部分，实现曲率半径超过3nm的增加，而不会使风险 在槽分离结构中的上槽边缘部分处或附近在基板表面上产生任何水平差。 这消除了晶体管泄漏电流的增加或由于栅极电极膜的端部附近或周围的局部电场浓度而导致的耐压特性的降低，这进而导致提高使用的晶体管的电可靠性的能力 。

公开(公告)号：US06562695B1

公开(公告)日：2003-05-13

申请号：US09889018

申请日：2001-07-10

申请人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

发明人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

IPC分类号： H01L2176

CPC分类号： H01L21/76229 ,  H01L21/76224 ,  H01L21/76232 ,  H01L27/10852 ,  H01L28/91

摘要： Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.

摘要翻译： 通过使用氮化硅膜和侧壁间隔物作为掩模的干蚀刻将沟槽限定在具有器件隔离区的衬底中。 此后，除去位于氮化硅膜侧壁上的侧壁隔离物，并对衬底进行热氧化，由此在每个有源区的周边部分的衬底表面进行所谓的圆形处理，以便 具有凸形圆形的截面形状。

公开(公告)号：US07397104B2

公开(公告)日：2008-07-08

申请号：US10778081

申请日：2004-02-17

申请人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

发明人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

IPC分类号： H01L21/00

CPC分类号： H01L21/76229 ,  H01L21/76224 ,  H01L21/76232 ,  H01L27/10852 ,  H01L28/91

摘要： A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.

摘要翻译： 提供一种半导体集成电路器件，其包括有源区，与有源区相邻的浅槽隔离，以及形成在有源区中并具有栅极的半导体元件。 有源区的宽度和浅槽隔离的宽度的和构成栅极的栅极宽度方向上的最小间距，并且有源区的宽度被设定为大于最小间距的一半 。

公开(公告)号：US06720234B2

公开(公告)日：2004-04-13

申请号：US10366423

申请日：2003-02-14

申请人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

发明人： Norio Suzuki ,  Hiroyuki Ichizoe ,  Masayuki Kojima ,  Keiji Okamoto ,  Shinichi Horibe ,  Kozo Watanabe ,  Yasuko Yoshida ,  Shuji Ikeda ,  Akira Takamatsu ,  Norio Ishitsuka ,  Atsushi Ogishima ,  Maki Shimoda

IPC分类号： H01L2176

CPC分类号： H01L21/76229 ,  H01L21/76224 ,  H01L21/76232 ,  H01L27/10852 ,  H01L28/91

摘要： Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.

摘要翻译： 通过使用氮化硅膜和侧壁间隔物作为掩模的干蚀刻将沟槽限定在具有器件隔离区的衬底中。 此后，除去位于氮化硅膜侧壁上的侧壁隔离物，并对衬底进行热氧化，由此在每个有源区的周边部分的衬底表面进行所谓的圆形处理，以便 具有凸形圆形的截面形状。

公开(公告)号：US06753231B2

公开(公告)日：2004-06-22

申请号：US10379543

申请日：2003-03-06

申请人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

发明人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

IPC分类号： H01L21336

CPC分类号： H01L27/105 ,  H01L27/1052

摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

摘要翻译： 提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。 为了设置驱动MISFET Qd的Vth，传输用于形成SRAM的存储单元的负载电阻QL的MISFET Qt和MISFET相对有意地高于SRAM外围电路和诸如微处理器的逻辑电路的预定MISFET的Vth，杂质 介绍引入步骤，用于设置驱动MISFET Qd的Vth，用于负载电阻的传输MISFET Qt和MISFET，与用于设置预定MISFET的Vth的杂质引入步骤分开。

公开(公告)号：US06559006B2

公开(公告)日：2003-05-06

申请号：US10157978

申请日：2002-05-31

申请人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

发明人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

IPC分类号： H01L218242

CPC分类号： H01L27/105 ,  H01L27/1052

摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

摘要翻译： 提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。 为了设置驱动MISFET Qd的Vth，传输用于形成SRAM的存储单元的负载电阻QL的MISFET Qt和MISFET相对有意地高于SRAM外围电路和诸如微处理器的逻辑电路的预定MISFET的Vth，杂质 介绍引入步骤，用于设置驱动MISFET Qd的Vth，用于负载电阻的传输MISFET Qt和MISFET，与用于设置预定MISFET的Vth的杂质引入步骤分开。

公开(公告)号：US06436753B1

公开(公告)日：2002-08-20

申请号：US09372007

申请日：1999-08-11

申请人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

发明人： Shuji Ikeda ,  Yasuko Yoshida ,  Masayuki Kojima ,  Kenji Shiozawa ,  Mitsuyuki Kimura ,  Norio Nakagawa ,  Koichiro Ishibashi ,  Yasuhisa Shimazaki ,  Kenichi Osada ,  Kunio Uchiyama

IPC分类号： H01L218244

CPC分类号： H01L27/105 ,  H01L27/1052

摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits, such as a microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

摘要翻译： 提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。 为了设置驱动MISFET Qd的Vth，对于形成SRAM的存储单元的负载电阻QL的转移MISFET Qt和MISFET相对有意地高于诸如微处理器的SRAM外围电路和逻辑电路的预定MISFET的Vth， 引入杂质引入步骤，用于设置用于设置预定MISFET的Vth的杂质引入步骤的驱动MISFET Qd，负载电阻的转移MISFET Qt和MISFET的Vth。

公开(公告)号：US06512245B2

公开(公告)日：2003-01-28

申请号：US09859045

申请日：2001-05-17

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Kyoichiro Asayama ,  Eri Fujita ,  Koichiro Ishibashi ,  Toshiro Aoto ,  Sadayuki Morita ,  Atsuyoshi Koike ,  Masayuki Kojima ,  Yasuo Kiguchi ,  Kazuyuki Suko ,  Fumiyuki Kanai ,  Naotaka Hashimoto ,  Toshiaki Yamanaka

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Kyoichiro Asayama ,  Eri Fujita ,  Koichiro Ishibashi ,  Toshiro Aoto ,  Sadayuki Morita ,  Atsuyoshi Koike ,  Masayuki Kojima ,  Yasuo Kiguchi ,  Kazuyuki Suko ,  Fumiyuki Kanai ,  Naotaka Hashimoto ,  Toshiaki Yamanaka

IPC分类号： H01L2972

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.

摘要翻译： 一种静态随机存取存储器，包括由字线控制的转移MISFET和由驱动器MISFET和负载MISFET构成的触发电路组成的存储单元。 负载MISFET的顶部覆盖有电源电压线，使得层叠结构的电容器元件形成在负载MISFET的栅电极和电源电压线之间。

公开(公告)号：US06307217B1

公开(公告)日：2001-10-23

申请号：US08181545

申请日：1994-01-14

申请人： Shuji Ikeda ,  Satoshi Meguro ,  Kyoichiro Asayama ,  Eri Fujita ,  Koichiro Ishibashi ,  Toshiro Aoto ,  Sadayuki Morita ,  Atsuyoshi Koike ,  Masayuki Kojima ,  Yasuo Kiguchi ,  Kazuyuki Suko ,  Fumiyuki Kanai ,  Naotaka Hashimoto ,  Toshiaki Yamanaka

发明人： Shuji Ikeda ,  Satoshi Meguro ,  Kyoichiro Asayama ,  Eri Fujita ,  Koichiro Ishibashi ,  Toshiro Aoto ,  Sadayuki Morita ,  Atsuyoshi Koike ,  Masayuki Kojima ,  Yasuo Kiguchi ,  Kazuyuki Suko ,  Fumiyuki Kanai ,  Naotaka Hashimoto ,  Toshiaki Yamanaka

IPC分类号： H01L2972

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

摘要： A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.

摘要翻译： 一种静态随机存取存储器，包括由字线控制的转移MISFET和由驱动器MISFET和负载MISFET构成的触发电路组成的存储单元。 负载MISFET的顶部覆盖有电源电压线，使得层叠结构的电容器元件形成在负载MISFET的栅电极和电源电压线之间。