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    Method for manufacturing semiconductor device
    1.
    发明授权
    Method for manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US6090684A

    公开(公告)日：2000-07-18

    申请号：US363184

    申请日：1999-07-29

    申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Masayuki Kojima ,  Kota Funayama

    发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Masayuki Kojima ,  Kota Funayama

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L29/78

    CPC分类号： H01L21/76232 ,  Y10S148/05

    摘要： A shallow groove isolation structure (SGI) electrically insulates adjoining transistors on a semiconductor substrate. A pad oxide film is formed on the semiconductor substrate and an oxidation inhibition film is formed on the pad oxide film. Parts of the oxide inhibition film and pad oxide film are removed to form the groove. In particular, the pad oxide film is removed from an upper edge of the groove within a range of 5 to 40 nm. A region of the groove is oxidized in an oxidation environment with a cast ratio of hydrogen (H.sub.2) to oxygen (O.sub.2) being less than or equal to 0.5. At this ratio, the oxidizing progresses under low stress at the upper groove edges of the substrate thereby enabling rounding of the upper groove edges without creating a level difference at or near the upper groove edge on the substrate surface.

    摘要翻译： 浅沟隔离结构（SGI）使半导体衬底上的相邻晶体管电绝缘。 在半导体基板上形成衬垫氧化膜，在衬垫氧化膜上形成氧化抑制膜。 除去氧化物抑制膜和垫氧化膜的一部分以形成槽。 特别地，在5〜40nm的范围内，从槽的上边缘去除衬垫氧化膜。 凹槽的区域在氢（H 2）与氧（O 2）的铸造比小于或等于0.5的氧化环境中被氧化。 在该比例下，在基板的上槽边缘处的低应力下氧化进行，从而能够在上槽边缘的四舍五入，而不会在基板表面上的上槽边缘处或附近产生水平差。

    Method for manufacturing semiconductor device
    2.
    发明授权
    Method for manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06403446B1

    公开(公告)日：2002-06-11

    申请号：US09536447

    申请日：2000-03-28

    申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Masayuki Kojima ,  Kota Funayama

    发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Masayuki Kojima ,  Kota Funayama

    IPC分类号： H01L2176

    CPC分类号： H01L21/76232 ,  Y10S148/05

    摘要： Manufacturing a semiconductor device avoiding an increase of transistor leak current or reduction of the withstanding voltage characteristics is by at least one of: The pad oxide film is removed along the substrate surface from the upper edge of the groove over a distance ranging from 5 to 40 nm: The exposed surface of the semiconductor substrate undergoes removal by isotropic etching within 20 nm; and oxidizing a groove portion formed in a semiconductor substrate in an oxidation environment with a gas ratio of hydrogen (H2) to oxygen (O2) being less than or equal to 0.5, an increase of the curvature radius beyond 3nm is achieved without associating the risk of creation of any level difference on the substrate surface at or near the upper groove edge portions in a groove separation structure. This eliminates either an increase of transistor leak current or reduction of the withstanding voltage characteristics thereof otherwise occurring due to local electric field concentration near or around the terminate ends of a gate electrode film which in turn leads to an ability to improve electrical reliability of transistors used.

    摘要翻译： 制造半导体器件避免晶体管泄漏电流的增加或耐压特性的降低是至少以下之一：衬垫氧化膜沿着衬底表面从沟槽的上边缘移除5至40的距离 nm：通过各向同性蚀刻在20nm内去除半导体衬底的暴露表面; 并且在氧（H2）与氧气（O2）的气体比小于或等于0.5的氧化环境中氧化形成在半导体衬底中的沟槽部分，实现曲率半径超过3nm的增加，而不会使风险 在槽分离结构中的上槽边缘部分处或附近在基板表面上产生任何水平差。 这消除了晶体管泄漏电流的增加或由于栅极电极膜的端部附近或周围的局部电场浓度而导致的耐压特性的降低，这进而导致提高使用的晶体管的电可靠性的能力 。

    Process for producing semiconductor device and semiconductor device produced thereby
    5.
    发明授权
    Process for producing semiconductor device and semiconductor device produced thereby 失效
    由此生产半导体器件和半导体器件的方法

    公开(公告)号：US06858515B2

    公开(公告)日：2005-02-22

    申请号：US10638485

    申请日：2003-08-12

    申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Kozo Watanabe ,  Kenji Kanamitsu

    发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Kozo Watanabe ,  Kenji Kanamitsu

    IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L29/06

    CPC分类号： H01L21/76232 ,  H01L29/0657

    摘要： A semiconductor device free from electric failure in transistors at upper trench edges can be produced by a simplified process comprising basic steps of forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation presention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film, etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; oxidizing the trench formed in the semiconductor substrate; embedding an embedding isolation film in the oxidized trench; removing the embedding isolation film formed on the oxidation prevention film; removing the oxidation prevention film formed on the circuit-forming side of the semiconductor substrate; and removing the pad oxide film formed on the circuit-forming side of the semiconductor substrate, where round upper trench edges with a curvature can be obtained, if necessary, by conducting isotropic etching of exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.

    摘要翻译： 在上沟槽边缘处的晶体管中没有电故障的半导体器件可以通过简化的工艺制造，包括在半导体衬底的电路形成侧形成衬垫氧化膜的基本步骤; 在衬垫氧化膜上形成氧化防止膜; 在期望的位置除去氧化呈现膜和衬垫氧化膜，从而暴露半导体衬底的表面; 水平地凹陷衬垫氧化膜，通过各向同性蚀刻蚀刻半导体衬底的暴露表面; 使用氧化防止膜作为掩模，形成期望深度的沟槽; 使衬垫氧化膜水平地凹陷; 氧化在半导体衬底中形成的沟槽; 在氧化沟槽中嵌入嵌入隔离膜; 去除形成在防氧化膜上的嵌入隔离膜; 去除形成在半导体衬底的电路形成侧的氧化防止膜; 以及去除形成在半导体衬底的电路形成侧的衬垫氧化膜，其中如果需要，可以获得具有曲率的圆形上沟槽边缘，通过对半导体衬底的暴露表面进行各向同性蚀刻并且使衬垫的水平凹陷 氧化膜在沟槽氧化之前，因此只需要一个氧化步骤。

    Semiconductor device having element isolation structure
    6.
    发明授权
    Semiconductor device having element isolation structure 失效
    具有元件隔离结构的半导体器件

    公开(公告)号：US06635945B1

    公开(公告)日：2003-10-21

    申请号：US09580953

    申请日：2000-05-30

    申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Kozo Watanabe ,  Kenji Kanamitsu

    发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Kozo Watanabe ,  Kenji Kanamitsu

    IPC分类号： H01L2900

    CPC分类号： H01L21/76232 ,  H01L29/0657

    摘要： A semiconductor device and process of forming the device are described. The process includes forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation prevention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film; etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; and oxidizing the trench formed in the semiconductor substrate. The produced device has round upper trench edges obtained by conducting isotropic etching of the exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.

    摘要翻译： 描述半导体器件和形成器件的工艺。 该工艺包括在半导体衬底的电路形成侧上形成衬垫氧化膜; 在衬垫氧化膜上形成氧化防止膜; 在期望的位置除去氧化防止膜和焊盘氧化膜，从而暴露半导体衬底的表面; 使衬垫氧化膜水平地凹陷; 通过各向同性蚀刻蚀刻半导体衬底的暴露表面; 使用氧化防止膜作为掩模，形成期望深度的沟槽; 使衬垫氧化膜水平地凹陷; 以及氧化在半导体衬底中形成的沟槽。 所制造的器件具有圆形的上沟槽边缘，其通过对半导体衬底的暴露表面进行各向同性蚀刻并在沟槽氧化之前水平凹陷焊盘氧化膜而获得，由此仅需要一个氧化步骤。

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06326255B1

    公开(公告)日：2001-12-04

    申请号：US09675053

    申请日：2000-09-29

    申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Michimasa Funabashi

    发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Michimasa Funabashi

    IPC分类号： H01L2126

    CPC分类号： H01L21/76224 ,  Y10S438/978

    摘要： A method for manufacturing a semiconductor device includes the steps of (1) forming a pad oxide film of 5 nm or more on a circuit forming surface of a semiconductor substrate; (2) forming an oxidation inhibition film on the pad oxide film; (3) forming grooves of a given depth with the oxidation inhibition film as a mask; (4) receding the pad oxide film; (5) oxidizing the grooves formed on the semiconductor substrate in the range of 0

    摘要翻译： 一种制造半导体器件的方法包括以下步骤：（1）在半导体衬底的电路形成表面上形成5nm以上的衬垫氧化膜; （2）在衬垫氧化膜上形成氧化抑制膜; （3）以氧化抑制膜为掩模形成给定深度的槽; （4）后退衬垫氧化膜; （5）在氧化气氛为干燥氧化（H2 /O2≈0）的0℃<0.88t-924的范围内对形成在半导体衬底上的沟槽进行氧化，对应于空气中的氧气分压 氧分压比为C％，氧化温度为t（℃）; （6）在氧化槽内埋入绝缘膜; （7）除去形成在氧化抑制膜上的埋置绝缘膜; （8）除去形成在半导体衬底的电路形成表面上的氧化抑制膜; 和（9）去除形成在所述半导体衬底的电路形成表面上的衬垫氧化膜。

    Method of forming a shallow groove isolation structure
    9.
    发明授权
    Method of forming a shallow groove isolation structure 有权
    形成浅槽隔离结构的方法

    公开(公告)号：US06284625B1

    公开(公告)日：2001-09-04

    申请号：US09434308

    申请日：1999-11-05

    申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Michimasa Funabashi

    发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Michimasa Funabashi

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224 ,  Y10S438/978

    摘要： A method for manufacturing a semiconductor device includes the steps of (1) forming a pad oxide film of 5 nm or more on a circuit forming surface of a semiconductor substrate; (2) forming an oxidation inhibition film on the pad oxide film; (3) forming grooves of a given depth with the oxidation inhibition film as a mask; (4) receding the pad oxide film; (5) oxidizing the grooves formed on the semiconductor substrate in the range of 0

    摘要翻译： 一种制造半导体器件的方法包括以下步骤：（1）在半导体衬底的电路形成表面上形成5nm以上的衬垫氧化膜; （2）在衬垫氧化膜上形成氧化抑制膜; （3）以氧化抑制膜为掩模形成给定深度的槽; （4）后退衬垫氧化膜; （5）在氧化气氛为干燥氧化（H2 /O2≈0）的0℃<0.88t-924的范围内对形成在半导体衬底上的沟槽进行氧化，对应于空气中的氧气分压 氧分压比为C％，氧化温度为t（℃）; （6）在氧化槽内埋入绝缘膜; （7）除去形成在氧化抑制膜上的埋置绝缘膜; （8）除去形成在半导体衬底的电路形成表面上的氧化抑制膜; 和（9）去除形成在所述半导体衬底的电路形成表面上的衬垫氧化膜。