公开(公告)号：US11282760B2

公开(公告)日：2022-03-22

申请号：US16660664

申请日：2019-10-22

Applicant: Obsidian Sensors, Inc.

Inventor： Yaoling Pan ,  Tallis Young Chang ,  John Hyunchul Hong

IPC: H01L23/31 ,  B81C1/00 ,  B81B7/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/12 ,  H01L33/52 ,  H01L33/62 ,  H01L51/00 ,  H01L51/52 ,  H01L51/56

Abstract: This disclosure provides devices and methods for 3-D device packaging with backside interconnections. One or more device elements can be hermetically sealed from an ambient environment, such as by vacuum lamination and bonding. One or more via connections provide electrical interconnection from a device element to a back side of a device substrate, and provide electrical interconnection from the device substrate to external circuitry on the back side of the device. The external circuitry can include a printed circuit board or flex circuit. In some implementations, an electrically conductive pad is provided on the back side, which is electrically connected to at least one of the via connections. In some implementations, the one or more via connections are electrically connected to one or more electrical components or interconnections, such as a TFT or a routing line.

公开(公告)号：US10453766B2

公开(公告)日：2019-10-22

申请号：US15351180

申请日：2016-11-14

Applicant: OBSIDIAN SENSORS, INC.

Inventor： Yaoling Pan ,  Tallis Young Chang ,  John Hyunchul Hong

IPC: H01L51/56 ,  H01L23/31 ,  B81B7/00 ,  B81C1/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/12 ,  H01L33/52 ,  H01L33/62 ,  H01L51/00 ,  H01L51/52

Abstract: This disclosure provides devices and methods for 3-D device packaging with backside interconnections. One or more device elements can be hermetically sealed from an ambient environment, such as by vacuum lamination and bonding. One or more via connections provide electrical interconnection from a device element to a back side of a device substrate, and provide electrical interconnection from the device substrate to external circuitry on the back side of the device. The external circuitry can include a printed circuit board or flex circuit. In some implementations, an electrically conductive pad is provided on the back side, which is electrically connected to at least one of the via connections. In some implementations, the one or more via connections are electrically connected to one or more electrical components or interconnections, such as a TFT or a routing line.

公开(公告)号：US20180138102A1

公开(公告)日：2018-05-17

申请号：US15351180

申请日：2016-11-14

Applicant: OBSIDIAN SENSORS, INC.

Inventor： Yaoling Pan ,  Tallis Young Chang ,  John Hyunchul Hong

IPC: H01L23/31 ,  H01L23/528 ,  H01L23/522 ,  H01L27/12 ,  H01L33/62 ,  H01L33/52 ,  H01L51/52 ,  B81B7/00 ,  H01L51/56 ,  H01L21/56 ,  H01L21/768 ,  H01L21/683 ,  H01L51/00 ,  B81C1/00

CPC classification number: H01L23/3121 ,  B81B7/0058 ,  B81C1/00238 ,  B81C1/00301 ,  B81C2203/0145 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3135 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/124 ,  H01L33/52 ,  H01L33/62 ,  H01L51/003 ,  H01L51/5203 ,  H01L51/5253 ,  H01L51/56 ,  H01L2933/005 ,  H01L2933/0066

Abstract: This disclosure provides devices and methods for 3-D device packaging with backside interconnections. One or more device elements can be hermetically sealed from an ambient environment, such as by vacuum lamination and bonding. One or more via connections provide electrical interconnection from a device element to a back side of a device substrate, and provide electrical interconnection from the device substrate to external circuitry on the back side of the device. The external circuitry can include a printed circuit board or flex circuit. In some implementations, an electrically conductive pad is provided on the back side, which is electrically connected to at least one of the via connections. In some implementations, the one or more via connections are electrically connected to one or more electrical components or interconnections, such as a TFT or a routing line.

公开(公告)号：US11685649B2

公开(公告)日：2023-06-27

申请号：US16982519

申请日：2019-03-20

Applicant: Obsidian Sensors, Inc.

Inventor： John Hong ,  Tallis Chang ,  Edward Chan ,  Bing Wen ,  Yaoling Pan ,  Kenji Nomura

IPC: B81C1/00 ,  B81B7/00 ,  G01J5/20

CPC classification number: B81C1/00269 ,  B81B7/0038 ,  B81C1/00285 ,  B81C2203/019 ,  B81C2203/0118 ,  B81C2203/035 ,  B81C2203/05 ,  G01J5/20

Abstract: A method of manufacturing MEMS housings includes: providing glass spacers; providing a window plate; attaching the window plate to the glass spacers; aligning the glass spacers with a device glass plate having MEMS devices thereon; bonding the glass spacers to the device glass plate; and singulating the glass spacers, window plate, and device glass plate to produce the MEMS housings.

公开(公告)号：US10150667B2

公开(公告)日：2018-12-11

申请号：US15431725

申请日：2017-02-13

Applicant: OBSIDIAN SENSORS, INC.

Inventor： Yaoling Pan ,  Omar Bchir

IPC: B81B7/00 ,  B81C1/00

Abstract: Conventional package for integration of MEMS and electronics suffer from profiles that are undesirably high to due to the thickness of the glass. Also in conventional package manufacturing, the MEMS and electronic devices are first individualized, and the individualized MEMS and electronics are combined into a package, and thus can be costly. To address these and other disadvantages, a panel level packaging is proposed. In this proposal, plural MEMS devices are integrated with plural semiconductor devices at a panel level, and the panel is then individualized into separate packages.

公开(公告)号：US12006209B2

公开(公告)日：2024-06-11

申请号：US16980792

申请日：2019-03-14

Applicant: Obsidian Sensors, Inc.

Inventor： John Hong ,  Tallis Chang ,  Edward Chan ,  Bing Wen ,  Yaoling Pan ,  Sean Andrews

IPC: B81B3/00 ,  B81C1/00 ,  G01J5/20

CPC classification number: B81C1/00595 ,  B81B3/0081 ,  B81C1/0069 ,  G01J5/20 ,  B81B2201/0207 ,  B81B2203/019 ,  B81C2201/0105 ,  B81C2201/014

Abstract: A method of manufacturing an electromechanical systems structure includes manufacturing sub-micron structural features. In some embodiments, the structural features are less than the lithographic limit of a lithography process.