Deep N-well driven ramp buffer
    2.
    发明授权

    公开(公告)号:US12302025B2

    公开(公告)日:2025-05-13

    申请号:US18167665

    申请日:2023-02-10

    Abstract: A local ramp buffer includes a deep N− well layer disposed in a P− substrate beneath a surface of the P− substrate, a P− well disposed between the surface of the P− substrate and the deep N− well layer, and an N− well structure disposed in the P− substrate and coupled to the deep N− well layer. The N− well structure is disposed between the surface of the P− substrate and the deep N− well layer. The P− well is disposed inside an opening in the N− well structure. The N− well structure and the deep N− well layer are configured to isolate the P− well within the opening. A source follower transistor is disposed in the P− well. The source follower transistor includes a gate terminal coupled to the N− well structure and a ramp generator.

    TRIMMING CONTROL CIRCUIT FOR CURRENT INTEGRATION RAMP DAC SETTLING ASSIST CIRCUIT

    公开(公告)号:US20230336889A1

    公开(公告)日:2023-10-19

    申请号:US17719602

    申请日:2022-04-13

    CPC classification number: H04N5/378 H03K4/08 H04N5/3765

    Abstract: A ramp generator includes an operational amplifier having an output to generate a ramp signal. An integration current source is coupled to a first input and a reference voltage is coupled to a second input of the operational amplifier. A feedback capacitor is coupled between the first input and the output of the operational amplifier. A monitor circuit is coupled to the first and second inputs of the operational amplifier to generate an output flag in response to a comparison of the first and second inputs. A trimming control circuit is configured to generate a trimming signal in response to the output flag. An assist current source is configured to conduct an assist current from the output of the operational amplifier to ground in response the trimming signal generated by the trimming control circuit.

    DEEP N- WELL DRIVEN RAMP BUFFER
    7.
    发明公开

    公开(公告)号:US20240276124A1

    公开(公告)日:2024-08-15

    申请号:US18167665

    申请日:2023-02-10

    CPC classification number: H04N25/78 H04N25/77

    Abstract: A local ramp buffer includes a deep N− well layer disposed in a P− substrate beneath a surface of the P− substrate, a P− well disposed between the surface of the P− substrate and the deep N− well layer, and an N− well structure disposed in the P− substrate and coupled to the deep N− well layer. The N− well structure is disposed between the surface of the P− substrate and the deep N− well layer. The P− well is disposed inside an opening in the N− well structure. The N− well structure and the deep N− well layer are configured to isolate the P− well within the opening. A source follower transistor is disposed in the P− well. The source follower transistor includes a gate terminal coupled to the N− well structure and a ramp generator.

    Image sensors with improved negative pump voltage settling, and circuitry for the same

    公开(公告)号:US12034368B1

    公开(公告)日:2024-07-09

    申请号:US18174442

    申请日:2023-02-24

    CPC classification number: H02M3/071 G05F1/465 G05F3/205 H02M1/0045

    Abstract: Image sensors with improved negative pump voltage settling, and circuitry for the same, are disclosed herein. In one embodiment, a power supply settling circuit includes a negative charge pump and a reference voltage generator. An output of the negative charge pump is selectively coupled to a first node of the negative pump settling circuit via a first switch, and an output of the reference voltage generator is selectively coupled to a second node of the negative pump settling circuit via a second switch. The first node is further selectively coupled to ground via a third switch, and the second node is further selectively coupled to ground via a fourth switch. The first node can additionally be coupled to a first pad, and the second node can additionally be coupled to a second pad. The pads can each be coupled to a capacitor, such as an off-chip capacitor.

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