公开(公告)号：US5222110A

公开(公告)日：1993-06-22

申请号：US828931

申请日：1992-01-31

申请人： Otto Holzinger ,  Wolfgang Borst ,  Martin Klenk ,  Wolfgang Loewl ,  Erich Breuser ,  Thomas Goelzer ,  Otto Karl ,  Martin Streib ,  Mathias Lohse ,  Frieder Keller

发明人： Otto Holzinger ,  Wolfgang Borst ,  Martin Klenk ,  Wolfgang Loewl ,  Erich Breuser ,  Thomas Goelzer ,  Otto Karl ,  Martin Streib ,  Mathias Lohse ,  Frieder Keller

IPC分类号： F02D45/00 ,  F02P5/15 ,  G06F7/62 ,  G06F7/68

CPC分类号： G06F7/62 ,  G06F7/68

摘要： The electronic counter for counting a periodic clock signal generated at a preset clock frequency (f.sub.o) includes a clock circuit generating the periodic clock signal at the preset clock frequency (f.sub.o); an adjustable frequency divider (4) having an output (8), a first input (5) and a second input (7), the first input of the frequency divider (4) being connected to the clock circuit (6) so as to receive the periodic clock signal and the second input (7) of the frequency divider being connected to receive a cycle speed signal (n), the frequency divider (4) containing means to produce a pulsed output signal at a divider output frequency (c.sub.o); a tracking circuit (T) connected to the output (8) of the frequency divider (4) to receive the pulsed output signal at the divider output frequency (c.sub.o) and having a correction signal input for receiving a positive or negative correction signal (KS), the tracking circuit (T) acting to add a number of additional pulses to the pulsed output signal received thereby when the correcting signal is positive and suppressing a number of the pulses of the pulsed output signal from the frequency divider when the correcting signal is negative; and a counting circuit (14) having an output and connected to the tracking circuit (T) to count the pulses received from the tracking circuit and to generate a counter reading (z.sub.s). The divider output frequency (c.sub.o) is substantially equal to the clock frequency (f.sub.o) divided by a factor (T) equal to a constant (K) depending on the frequency divider (4) and the cycle speed signal (n).

摘要翻译： PCT No.PCT / DE90 / 00524 Sec。 371日期：1992年1月31日 102（e）日期1992年1月31日PCT提交1990年7月12日PCT公布。 出版物WO91 / 03015 日期：1991年3月7日。用于计数以预设时钟频率（fo）产生的周期性时钟信号的电子计数器包括以预设时钟频率（fo）产生周期性时钟信号的时钟电路。 具有输出（8），第一输入（5）和第二输入（7）的可调分频器（4），分频器（4）的第一输入端连接到时钟电路（6），以便 接收所述周期时钟信号，并且所述分频器的第二输入端（7）被连接以接收周期速度信号（n），所述分频器（4）包含用于以分频器输出频率（co）产生脉冲输出信号的装置， ; 连接到分频器（4）的输出（8）的跟踪电路（T），以分频器输出频率（co）接收脉冲输出信号，并具有用于接收正或负校正信号（KS ），当校正信号为正时，跟踪电路（T）用于向其接收的脉冲输出信号增加多个附加脉冲，并且当校正信号为正时时，抑制来自分频器的脉冲输出信号的脉冲数 负; 以及具有输出并连接到跟踪电路（T）的计数电路（14）以对从跟踪电路接收的脉冲进行计数并产生计数器读数（zs）。 分频器输出频率（co）基于分频器（4）和周期速度信号（n）基本上等于时钟频率（fo）除以等于常数（K）的因子（T）。

公开(公告)号：US5105441A

公开(公告)日：1992-04-14

申请号：US343179

申请日：1989-03-07

申请人： Wolfgang Borst ,  Wolfgang Botzenhardt ,  Siegfried Dais ,  Otto Karl ,  Uwe Kiencke ,  Martin Litschel ,  Herbert Lohner

发明人： Wolfgang Borst ,  Wolfgang Botzenhardt ,  Siegfried Dais ,  Otto Karl ,  Uwe Kiencke ,  Martin Litschel ,  Herbert Lohner

IPC分类号： H04L25/02 ,  B60R16/02 ,  H04L12/40 ,  H04L25/28 ,  H04L25/34

CPC分类号： H04L25/0268

摘要： A device for potential-free transmission of dominant and recessive data bits in a bus system operating with bit-by-bit arbitration includes a series connection of a modulator, a galvanic separation circuit, and a demodulator. Data bits to be transmitted are scanned in the modulator at equidistant time intervals and are divided into two intermediate trains of data bits wherein the dominant bits alternate with the recessive bits. The two intermediate trains are applied to two input terminals of a galvanic separating device, and a demodulation is effected on the output side of the separating device.

摘要翻译： PCT No.PCT / DE88 / 00354 Sec。 371日期：1989年3月7日 102（e）日期1989年3月7日PCT Filed 1988年6月13日PCT Pub。 公开号WO89 / 00368 日期：1989年1月12日。用于通过逐位仲裁操作的总线系统中的主导和隐性数据位的无电势传输的装置包括调制器，电流隔离电路和解调器的串联连接。 要发送的数据位以等间隔的时间间隔在调制器中扫描，并被划分为数据位的两个中间列，其中主要位与隐性位交替。 将两个中间列车施加到电流分离装置的两个输入端，并且在分离装置的输出侧进行解调。

公开(公告)号：US4207846A

公开(公告)日：1980-06-17

申请号：US894335

申请日：1978-04-07

申请人： Wolfgang Borst ,  Winfried Klotzner ,  Ernst-Olav Pagel ,  Hermann Vetter

发明人： Wolfgang Borst ,  Winfried Klotzner ,  Ernst-Olav Pagel ,  Hermann Vetter

IPC分类号： F02P5/155 ,  F02P7/03 ,  F02P5/04

CPC分类号： F02P5/155 ,  F02P7/03 ,  Y02T10/46

摘要： To control the ignition timing in a multicylinder engine, the computer output signal which controls the current flow through the ignition coil for generating the spark in the first cylinder is delayed and then applied to the ignition coil controlling the spark in a subsequent cylinder. The computer output signal is delayed by passing through a shift register whose clock input is derived from a pulse generator generating a pulse for each predetermined incremental angular rotation of the crankshaft. If a single ignition coil and a distributor are used, the computer output signal and the delayed computer output signal are applied to an OR gate whose output controls a switch controlling the current through the ignition coil. When more than one ignition coil is used, the computer output signal is applied to a switch controlling the current through the first coil, the delayed computer output signal to a switch controlling the current to a second coil. Further delays may be furnished for a control of sparking in additional cylinders.

摘要翻译： 为了控制多缸发动机中的点火正时，控制通过点火线圈的电流在第一气缸中产生火花的计算机输出信号被延迟，然后施加到控制随后气缸中的火花的点火线圈。 计算机输出信号通过一个移位寄存器被延迟，该移位寄存器的时钟输入是从产生用于曲轴的每个预定增量角旋转的脉冲的脉冲发生器导出的。 如果使用单个点火线圈和分配器，则计算机输出信号和延迟的计算机输出信号被施加到OR门，其输出控制开关控制通过点火线圈的电流。 当使用多于一个点火线圈时，计算机输出信号被施加到控制通过第一线圈的电流的开关，延迟的计算机输出信号到控制到第二线圈的电流的开关。 可以提供进一步的延迟来控制额外的气缸中的火花。

公开(公告)号：US4198936A

公开(公告)日：1980-04-22

申请号：US888194

申请日：1978-03-20

申请人： Ernst O. Pagel ,  Wolfgang Borst

发明人： Ernst O. Pagel ,  Wolfgang Borst

IPC分类号： F02P3/045 ,  H03K3/015 ,  F02P5/04 ,  F02P1/00 ,  G06F7/385

CPC分类号： F02P3/0456 ,  H03K3/015

摘要： A pulse train of a first frequency is generated, for example representative of speed of an internal combustion engine, and counted in a counter in a first counting cycle until the counter reaches a predetermined count number, the counter then being reset; a second frequency signal, for example a multiplied frequency derived from the first is then applied to the counter during a second count cycle, the counter stopping to count when current flow through the ignition coil of a predetermined level is sensed, and establishing a count number from which the counter can start counting at the next subsequent first cycle. The ON time of ignition current flow is controlled to commence at the beginning of the second count cycle, terminating at the ignition instant, as controlled by an ignition time control arrangement.

摘要翻译： 产生第一频率的脉冲串，例如表示内燃机的速度，并且在第一计数周期内在计数器中计数，直到计数器达到预定计数值，计数器然后被复位; 第二频率信号，例如从第一频率导出的相乘频率然后在第二计数周期中被施加到计数器，当检测到电流流过预定电平的点火线圈的计数器停止计数，并建立计数 计数器从该计数器可以在下一个第一个循环开始计数。 点火电流的接通时间被控制为在第二计数周期开始时开始，在点火时刻终止，由点火时间控制装置控制。

公开(公告)号：US4099507A

公开(公告)日：1978-07-11

申请号：US669814

申请日：1976-03-24

申请人： Ernst-Olav Pagel ,  Wolfgang Borst

发明人： Ernst-Olav Pagel ,  Wolfgang Borst

IPC分类号： F02P3/04 ,  F02D41/36 ,  F02P3/045 ,  F02P5/15 ,  F02P5/04

CPC分类号： F02D41/365 ,  F02P5/15 ,  Y02T10/46

摘要： To permit real-time counting of pulses representative of operating parameters of a moving body, for example in an internal combustion engine to control the ignition timing as a function of speed and other parameters in which, upon increase in speed of the engine, the ignition pulses follow each other rapidly and to permit sufficient current flow through the ignition coil for proper ignition, pulse sequences derived from the engine, for example as a function of speed, are converted into a higher frequency and the original pulses and the higher frequency are supplied to the counter as pulse trains so that the counter will reach the appropriate count state for which the ignition angle is to be computed at a time sufficiently in advance of the triggering of the ignition current, so that the time available for flow of ignition current will be increased, even at high engine speeds. Two pulse trains, differing in frequency and length, are applied to the counter, the counter being set for each triggering or ignition pulse to a predetermined value by a count angle computer stage, the pulse duration and cycling duration of the pulse voltage being determined by the counting time below and above a certain count state of the counter.

摘要翻译： 为了允许代表移动体的操作参数的脉冲的实时计数，例如在内燃机中，根据速度和其它参数来控制点火正时，其中在发动机的速度增加时，点火 脉冲快速跟随，并允许足够的电流流过点火线圈以进行适当点火，从发动机得到的脉冲序列（例如作为速度的函数）被转换为更高的频率，并且提供原始脉冲和较高频率 作为脉冲串使计数器达到适当的计数状态，在点火电流的触发之前充分地计算点火角度，从而使点火电流流动的时间 即使在高发动机转速下也能增加。 频率和长度不同的两个脉冲串被施加到计数器，计数器通过计数角计算机级为每个触发或点火脉冲设置为预定值，脉冲电压的脉冲持续时间和循环持续时间由 计数时间低于和高于计数器的某个计数状态。

公开(公告)号：US5099810A

公开(公告)日：1992-03-31

申请号：US573191

申请日：1990-08-27

申请人： Wolfgang Borst

发明人： Wolfgang Borst

IPC分类号： F02B75/02 ,  F02D45/00 ,  F02P3/045 ,  F02P7/077

CPC分类号： F02P7/077 ,  F02P3/0453 ,  F02B2075/027

摘要： A device for controlling ignition and/or injection operations in a four-stroke internal combustion engine comprises a phase-locked loop (PLL) in which a frequency divider (14) divides the number of peaks of a triangular output waveform (w) by half the number of cylinders to produce a feedback signal which is compared in a phase comparator (10) with reference marks (BM) produced by a pulse generator associated on the engine crankshaft. The rotation of the crankshaft is thereby accurately divided into the required number of segments for the spark plugs of the individual cylinders. The speed-dependent capacitor (C.sub.n) is charged or discharged upon an increase or decrease in speed (n) by means of a follower control (18), to adjust the output frequency of the waveform (w) so that it remains in synchronism with the reference marks (BM). The phase of the output waveform (w) is corrected upon an increase or decrease in speed (n) by the follower control (18) which either multiplies the current (i.sub.w) to charge the output capacitor (C.sub.w) rapidly in a fraction of the period of the waveform upon an increase in speed (n) or sets the current (i.sub.w) at zero so that the output capacitor (C.sub.w) temporarily holds its charge upon a decrease in speed (n).

摘要翻译： PCT No.PCT / EP88 / 00146 Sec。 371日期1990年8月27日第 102（e）日期1990年8月27日PCT提交1988年2月27日PCT公布。 公开号WO89 / 08186 日本1989年9月8日。一种用于控制四冲程内燃机中的点火和/或喷射操作的装置，包括锁相环（PLL），其中分频器（14）将三角形的峰值数 输出波形（w）乘以气缸数量的一半，以产生在相位比较器（10）中与由发动机曲轴相关联的脉冲发生器产生的参考标记（BM）进行比较的反馈信号。 因此，曲轴的旋转被精确地分成用于各个气缸的火花塞的所需数量的段。 速度依赖电容器（Cn）通过跟随器控制器（18）在速度（n）的增加或减小时进行充电或放电，以调整波形（w）的输出频率，使其保持与 参考标记（BM）。 输出波形（w）的相位通过跟随器控制器（18）的速度（n）的增加或减小来校正，所述跟随器控制器（18）将电流（iw）相乘以使输出电容器（Cw）在一小部分中快速充电 在速度（n）增加时的波形周期或将电流（iw）设置为零，使得输出电容器（Cw）在速度（n）的降低时临时保持其电荷。

公开(公告)号：US4063539A

公开(公告)日：1977-12-20

申请号：US650971

申请日：1976-01-21

申请人： Ingo Gorille ,  Wolfgang Borst ,  Winfried Klotzner ,  Karl Ott ,  Heinz Moller ,  Gunter Honig ,  Uwe Kiencke ,  Martin Zechnall ,  Ulrich Flaig ,  Alfred Schulz ,  Ernst-Olav Pagel

发明人： Ingo Gorille ,  Wolfgang Borst ,  Winfried Klotzner ,  Karl Ott ,  Heinz Moller ,  Gunter Honig ,  Uwe Kiencke ,  Martin Zechnall ,  Ulrich Flaig ,  Alfred Schulz ,  Ernst-Olav Pagel

IPC分类号： F02B1/04 ,  F02P5/15 ,  F02P7/077 ,  G05B11/36 ,  F02B5/02

CPC分类号： F02P5/15 ,  F02P7/0775 ,  F02B1/04 ,  Y02T10/46

摘要： Operating parameters, such as speed and loading of the engine are converted in electrical signals which are converted into pulse rates, to control counting of an address counter, addressing a read-only (ROM) memory in which characteristics of the engine are stored. To provide easy introduction of additional parameters such as temperature, idle condition, maximum speed, start condition, etc., the final value of an accumulator counter, the number of which at a given time controls the ignition timing, can be changed; further, to simplify the system, the speed and load signals are processed during a portion of the time between successive ignition events, the remaining portion of the time being controlled solely by one of the parameters (preferably speed), thus simplifying the circuitry by providing a transfer switch connecting for the remaining period only the selected (preferably speed) signal to the accumulator counter, the count state of which controls the ignition instant.

摘要翻译： 诸如发动机的速度和负载的操作参数被转换成转换成脉冲速率的电信号，以控制地址计数器的计数，寻址存储发动机特性的只读（ROM）存储器。 为了简单地引入诸如温度，怠速条件，最大速度，启动条件等附加参数，可以改变在给定时间控制点火正时的累加器计数器的最终值; 此外，为了简化系统，速度和负载信号在连续点火事件之间的一段时间内被处理，剩余部分时间仅由参数之一（最好是速度）控制，从而通过提供 一个转换开关，将余下的时间段仅连接到累加器计数器，其计数状态控制点火时刻。

公开(公告)号：US4088106A

公开(公告)日：1978-05-09

申请号：US718528

申请日：1976-08-30

申请人： Wolfgang Borst ,  Karl Ott

发明人： Wolfgang Borst ,  Karl Ott

IPC分类号： F02P3/055 ,  F02P9/00

CPC分类号： F02P3/0558

摘要： A speed related signal is counted out with respect to clock pulses having a predetermined rate in a counter; if, and when the counter reaches a certain predetermined number, the number is decoded and applied as a disconnect control signal to open a switch controlling current flow through the ignition coil. The number is selected to occur only if the engine operates at a very slow speed, or is stopped, so that no reset signal will be applied to the counter. A logic stage is provided having both the output of the count decoder stage as well as of the speed related signal applied thereto to ensure that disconnection is effected only when the counter has reached the decoding number, and then to continue reliably disconnection of the ignition current.

摘要翻译： 在计数器中相对于具有预定速率的时钟脉冲计数速度相关信号; 如果并且当计数器达到一定的预定数量时，该数字被解码并作为断开控制信号施加，以打开控制通过点火线圈的电流的开关。 只有当发动机以非常慢的速度运行或停止运行时才选择该数字，以便不会将复位信号应用于计数器。 提供具有计数解码器级的输出和施加到其的速度相关信号的逻辑级，以确保仅当计数器已经达到解码号时才进行断开，然后继续可靠地断开点火电流 。

公开(公告)号：US4078203A

公开(公告)日：1978-03-07

申请号：US721952

申请日：1976-09-10

申请人： Wolfgang Borst

发明人： Wolfgang Borst

IPC分类号： H03K23/64 ,  F02D41/04 ,  H03K23/66 ,  H03K21/00 ,  H03K23/06

CPC分类号： H03K23/662

摘要： To control the division ratio of an input frequency applied to a loop circuit including an adder, the overflow output of which is fed back to one of its inputs, the division denominator is applied to a comparator to be compared with the overflow output of the adder to select, in accordance with the comparison in the comparator, with respect to a selected denominator number, the frequency division, so that the output of the adder will be representative of a converted frequency as selected with respect to the denominator number.

摘要翻译： 为了控制施加到包括加法器的环路电路的输入频率的分频比，其溢出输出被反馈到其输入之一，分频分母被加到比较器以与加法器的溢出输出进行比较 根据比较器中的比较来选择相对于所选择的分母数字进行分频，使得加法器的输出将代表相对于分母数选择的转换频率。