公开(公告)号：US10672878B2

公开(公告)日：2020-06-02

申请号：US16255875

申请日：2019-01-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Ohoka ,  Nobuyuki Horikawa ,  Masao Uchida

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/16

Abstract: The silicon carbide semiconductor device includes a plurality of unit cells each having an MISFET structure and provided on a silicon carbide semiconductor substrate. A gate upper electrode disposed adjacent to the plurality of unit cells includes a gate pad and gate global wires. When viewed in plan, gate electrodes do not overlap with the gate pad.

公开(公告)号：US10748838B2

公开(公告)日：2020-08-18

申请号：US16255874

申请日：2019-01-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Ohoka ,  Nobuyuki Horikawa ,  Masao Uchida

IPC: H01L23/482 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/417

Abstract: A silicon carbide semiconductor device includes an upper gate electrode including a gate pad and a gate wiring line, and an upper source electrode including first and second source pads. The gate wiring line includes a gate global wiring line extending to encircle the source pads, and a gate connection wiring line. The upper source electrode includes an outer periphery source wiring line extending to encircle the gate global wiring line, and first and second source connections connecting the outer periphery source wiring line to the first and second source pads, respectively. The gate global wiring line includes a first portion, a second portion, and a third portion. The first portion is split at a first substrate corner and a second substrate corner and lies between the first substrate corner and the second substrate corner.

公开(公告)号：US09865591B2

公开(公告)日：2018-01-09

申请号：US15342023

申请日：2016-11-02

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Nobuyuki Horikawa ,  Osamu Kusumoto ,  Masashi Hayashi ,  Masao Uchida

IPC: H01L29/15 ,  H01L27/06 ,  H01L29/78 ,  H01L27/04 ,  H01L29/861 ,  H01L29/868 ,  H01L29/06 ,  H01L29/12 ,  H01L29/16 ,  H01L29/41

CPC classification number: H01L27/0605 ,  H01L27/04 ,  H01L27/0727 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/41 ,  H01L29/78 ,  H01L29/861 ,  H01L29/8611 ,  H01L29/868

Abstract: A silicon carbide semiconductor device includes a transistor region, a diode region, a gate line region, and a gate pad region. The gate pad region and the gate line region are each disposed to be sandwiched between the diode region and the diode region, and a gate electrode on the gate pad region and the gate line region is formed on an insulating film formed on an epitaxial layer. Thus, breakdown of the insulating film in the gate region can be prevented without causing deterioration in quality of the gate insulating film, upon switching and avalanche breakdown.

公开(公告)号：USRE49195E1

公开(公告)日：2022-08-30

申请号：US16294567

申请日：2019-03-06

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Nobuyuki Horikawa ,  Osamu Kusumoto ,  Masashi Hayashi ,  Masao Uchida

IPC: H01L27/04 ,  H01L29/06 ,  H01L29/78 ,  H01L29/861 ,  H01L29/868 ,  H01L29/12 ,  H01L29/16 ,  H01L29/41 ,  H01L27/06 ,  H01L27/07 ,  H01L29/66 ,  H01L29/423 ,  H01L29/739

Abstract: A silicon carbide semiconductor device includes a transistor region, a diode region, a gate line region, and a gate pad region. The gate pad region and the gate line region are each disposed to be sandwiched between the diode region and the diode region, and a gate electrode on the gate pad region and the gate line region is formed on an insulating film formed on an epitaxial layer. Thus, breakdown of the insulating film in the gate region can be prevented without causing deterioration in quality of the gate insulating film, upon switching and avalanche breakdown.

公开(公告)号：US09691759B2

公开(公告)日：2017-06-27

申请号：US15251886

申请日：2016-08-30

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masao Uchida ,  Nobuyuki Horikawa

IPC: H01L29/06 ,  H01L27/06 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/8213 ,  H01L27/0605 ,  H01L27/0727 ,  H01L29/1608 ,  H01L29/7827

Abstract: A semiconductor device includes a first silicon carbide semiconductor layer, a source including a source pad and a source wiring, a gate including a gate pad and a gate wiring, first unit cells disposed in a first element region, and second unit cells disposed in a second element region. In a plan view, the first and second element regions are adjacent to each other with the gate wiring between the first and second element regions. A first electrode including the gate electrode of each first unit cell is disposed in the first element region and electrically connected to the gate. A second electrode including the gate electrode of each second unit cell is disposed in the second element region and not electrically connected to the gate. The first and second electrodes are separated below the gate wiring.

公开(公告)号：US09923090B2

公开(公告)日：2018-03-20

申请号：US15403381

申请日：2017-01-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Atsushi Ohoka ,  Masao Uchida ,  Nobuyuki Horikawa ,  Osamu Kusumoto

IPC: H01L29/78 ,  H01L29/16 ,  H01L27/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/80

CPC classification number: H01L29/7803 ,  H01L21/28 ,  H01L27/0617 ,  H01L29/0696 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7828 ,  H01L29/80

Abstract: In the silicon carbide semiconductor element, a second silicon carbide semiconductor layer that is in contact with the surface of a first silicon carbide semiconductor layer has at least an upper layer including a dopant of a first conductivity type at a high concentration. Above a junction field effect transistor (JFET) region interposed between body regions that are disposed in the first silicon carbide semiconductor layer so as to be spaced from each other, the silicon carbide semiconductor element has a channel removed region, which is a cutout formed by removing a high concentration layer from the front surface side of the second silicon carbide semiconductor layer, the high concentration layer having a higher dopant concentration than at least the dopant concentration of the JFET region. The width of the channel removed region is smaller than that of the JFET region.

公开(公告)号：US09252211B2

公开(公告)日：2016-02-02

申请号：US14714226

申请日：2015-05-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masao Uchida ,  Osamu Kusumoto ,  Nobuyuki Horikawa

IPC: H01L29/15 ,  H01L29/745 ,  H01L21/00 ,  H01L21/338 ,  H01L29/06 ,  H01L27/06 ,  H01L29/872

CPC classification number: H01L29/0619 ,  H01L21/8213 ,  H01L27/0207 ,  H01L27/0605 ,  H01L27/0727 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/66068 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

Abstract: A semiconductor device includes a first silicon carbide semiconductor layer of a first conductive type that is positioned on a front surface of a substrate of the first conductive type, a transistor region that includes transistor cells, a Schottky region, and a boundary region. The boundary region includes a second body region and a gate connector that is arranged on the second body region via an insulating film and electrically connected with a gate electrode. The Schottky region includes a Schottky electrode that is arranged on the first silicon carbide semiconductor layer.

Abstract translation: 半导体器件包括位于第一导电类型的衬底的前表面上的第一导电类型的第一碳化硅半导体层，包括晶体管单元，肖特基区域和边界区域的晶体管区域。 边界区域包括第二体区域和栅极连接器，其经由绝缘膜布置在第二体区上并与栅电极电连接。 肖特基区域包括布置在第一碳化硅半导体层上的肖特基电极。