公开(公告)号：US20170263500A1

公开(公告)日：2017-09-14

申请号：US15426199

申请日：2017-02-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： BUNZI MIZUNO ,  SHOGO OKITA ,  MITSURU HIROSHIMA ,  TUTOMU SAKURAI ,  NORIYUKI MATSUBARA

IPC: H01L21/78 ,  H01L21/67

CPC classification number: H01L21/78 ,  H01J2237/334 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/67069 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/6831

Abstract: The method includes a laser scribing step of forming an opening including an exposing portion, where the first layer is exposed, by irradiating the dividing region of the substrate with laser light from the first main surface side, forming a remaining region on which the second layer in the dividing region remains around the opening other than the exposing portion, and forming a first damaged region of a surface layer portion of the first layer including the exposing portion and a second damaged region of a surface layer portion of the first layer to be covered by the remaining region on the first layer of the dividing region.

公开(公告)号：US20170263526A1

公开(公告)日：2017-09-14

申请号：US15427548

申请日：2017-02-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： BUNZI MIZUNO ,  MITSURU HIROSHIMA ,  SHOGO OKITA ,  NORIYUKI MATSUBARA ,  ATSUSHI HARIKAI

IPC: H01L23/31 ,  H01L21/78 ,  H01L21/428 ,  H01L21/56 ,  H01L21/311 ,  H01L23/544

CPC classification number: H01L23/3192 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/428 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2223/5446

Abstract: A method for manufacturing an element chip includes a protection film etching step of removing a part of the protection film which is stacked on the dividing region and the protection film which is stacked on the element region through etching the protection film anisotropically by exposing the substrate to first plasma and remaining the protection film for covering an end surface of the element region. Furthermore, the method for manufacturing an element chip includes an isotropic etching step of etching the dividing region isotropically by exposing the substrate to second plasma and a plasma dicing step of dividing the substrate to a plurality of element chips including the element region by exposing the substrate to third plasma in a state where the second main surface is supported by a supporting member.

公开(公告)号：US20170263525A1

公开(公告)日：2017-09-14

申请号：US15426341

申请日：2017-02-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： BUNZI MIZUNO ,  SHOGO OKITA ,  MITSURU HIROSHIMA ,  TUTOMU SAKURAI ,  NORIYUKI MATSUBARA

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/311 ,  H01L23/544 ,  H01L21/268 ,  H01L21/78

CPC classification number: H01L23/3192 ,  H01L21/268 ,  H01L21/31116 ,  H01L21/56 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L23/562 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381

Abstract: A method of manufacturing an element chip includes an isotropic etching step of removing the first damaged region and the second damaged region through etching the first layer isotropically by exposing the substrate to first plasma after the laser scribing step. The method of manufacturing an element chip further includes a plasma, dicing step of dividing the substrate to a plurality of element chips including the element region through etching the first layer anisotropically by exposing the substrate to second plasma in a state where the second main surface is supported by a supporting member, after the isotropic etching step.

公开(公告)号：US20170263524A1

公开(公告)日：2017-09-14

申请号：US15426181

申请日：2017-02-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： BUNZI MIZUNO ,  MITSURU HIROSHIMA ,  SHOGO OKITA ,  NORIYUKI MATSUBARA ,  ATSUSHI HARIKAI

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/311 ,  H01L23/544 ,  H01L21/268 ,  H01L21/78

CPC classification number: H01L23/3192 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/0337 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/56 ,  H01L21/67109 ,  H01L21/6831 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/544 ,  H01L23/562 ,  H01L2221/68327 ,  H01L2221/68381

Abstract: A method for manufacturing an element chip includes a protection film stacking step of staking a protection film to the element region, and the dividing region, the part of the exposed second damaged region and a protection film etching step of removing a part of the protection film which is stacked on the dividing region and the protection film which is stacked on the element region by exposing the substrate to second plasma and remaining the protection film for covering the part of the second damaged region. Furthermore, the method for manufacturing an element chip includes a plasma dicing step of dividing the substrate to a plurality of element chips by exposing the substrate to third plasma in a state where the second main surface is supported by a supporting member.

公开(公告)号：US20170263502A1

公开(公告)日：2017-09-14

申请号：US15428477

申请日：2017-02-09

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： SHOGO OKITA ,  ATSUSHI HARIKAI ,  AKIHIRO ITOU ,  NORIYUKI MATSUBARA ,  BUNZI MIZUNO

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/683 ,  H01L21/311 ,  H01L21/67

CPC classification number: H01L21/78 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/67069 ,  H01L21/67109 ,  H01L21/6831 ,  H01L21/6833 ,  H01L21/6836 ,  H01L21/68742 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/68381

Abstract: The method for manufacturing an element chip includes a mounting step and a plasma dicing step. In the mounting step, a semiconductor substrate with flexibility, which has a first main surface and a second main surface located at an opposite side of the first main surface, which has a plurality element regions and a dividing region for defining the element regions, and on which a mask for covering the first main surface in the element region and for exposing the first main surface in the dividing region is formed, is mounted on a stage. In the plasma dicing step, the semiconductor substrate is diced into a plurality of element chips including the element; region by exposing the first main surface side of the semiconductor substrate to plasma on the stage and etching from the first main surface side to the second main surface while forming a groove on the dividing region.

公开(公告)号：US20170263501A1

公开(公告)日：2017-09-14

申请号：US15427380

申请日：2017-02-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： BUNZI MIZUNO ,  SHOGO OKITA ,  NORIYUKI MATSUBARA ,  ATSUSHI HARIKAI ,  MITSURU HIROSHIMA

IPC: H01L21/78 ,  H01L29/30 ,  H01L23/31 ,  H01L21/56 ,  H01L21/311

CPC classification number: H01L21/78 ,  H01L21/311 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3171 ,  H01L23/3185 ,  H01L29/30

Abstract: A method for manufacturing an element chip includes a laser dicing step of dividing the substrate to a plurality of element chips including the element region by irradiating the dividing region of the substrate with laser light, in a state of supported by a supporting member and forming a damaged region on an end surface of the element chip. Furthermore, the method for manufacturing an element chip includes a protection film stacking step of stacking a protection film on the first main surface and the end surface of the element chip, after the laser dicing step and a protection film etching step of removing the protection film stacked on the first main surface through etching the protection film anisotropically by exposing the element chip to plasma, after the protection film stacking, step and remaining the protection film for covering the damaged region.