公开(公告)号：US20170263461A1

公开(公告)日：2017-09-14

申请号：US15427198

申请日：2017-02-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： NORIYUKI MATSUBARA ,  ATSUSHI HARIKAI ,  AKIHIRO ITOU

IPC: H01L21/3065 ,  H01L21/78 ,  H01L21/268 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L21/3065 ,  H01L21/268 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31133 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/6831 ,  H01L21/68742 ,  H01L21/68785 ,  H01L21/78

Abstract: A plasma processing method includes an attaching process of attaching a resin film to a first main surface of a substrate which is provided with the first main surface and a second main surface on an opposite side of the first main surface and a patterning process of forming a mask, which includes an opening exposing a region to be processed of the substrate, by patterning the resin film. The plasma processing method includes a first plasma process of generating first plasma of first gas in a depressurized atmosphere including the first gas, exposing the mask to the first plasma, and reducing a void between the mask and the first main surface. The plasma processing method includes a second plasma process of generating second plasma from second gas in atmosphere including the second gas, exposing the region to be processed exposed from the opening to the second plasma, and etching the region to be processed.

公开(公告)号：US20170229384A1

公开(公告)日：2017-08-10

申请号：US15408750

申请日：2017-01-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI HARIKAI ,  SHOGO OKITA ,  NORIYUKI MATSUBARA

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/563 ,  H01L21/78 ,  H01L21/784 ,  H01L23/3171 ,  H01L23/3185 ,  H01L24/09 ,  H01L24/89 ,  H01L2224/80801 ,  H01L2224/81 ,  H01L2924/15323

Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by insulating film, the substrate is divided into element chips by exposing the substrate to a first plasma, element chips having first surface, second surface, and side surface are held spaced from each other on carrier, insulating film is in a state of being exposed, recessed portions are formed by retreating insulating film by exposing element chips to second plasma for ashing, and then recessed portions are covered by protection films by third plasma for formation of the protection film, thereby suppressing creep-up of the conductive material to side surface in the mounting step.

公开(公告)号：US20180012802A1

公开(公告)日：2018-01-11

申请号：US15622250

申请日：2017-06-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： SHOGO OKITA ,  MITSURU HIROSHIMA ,  ATSUSHI HARIKAI ,  NORIYUKI MATSUBARA ,  AKIHIRO ITOU

IPC: H01L21/78 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/78 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31138

Abstract: A semiconductor chip manufacturing method includes preparing a semiconductor wafer including a front surface on which a bump is exposed, a rear surface located at a side opposite to the front surface, a plurality of element regions in each of which the bump is formed, and a dividing region defining each of the element regions, forming a mask which covers the bump and has an opening exposing the dividing region on the surface of the semiconductor wafer by spraying liquid which contains raw material of the mask along the bump by a spray coating method, and singulating the semiconductor wafer by exposing the surface of the semiconductor wafer to first plasma and etching the dividing region, which is exposed to the opening, until the rear surface is reached in a state where the bump is covered by the mask.

公开(公告)号：US20170229365A1

公开(公告)日：2017-08-10

申请号：US15408703

申请日：2017-01-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI HARIKAI ,  SHOGO OKITA ,  NORIYUKI MATSUBARA ,  MITSURU HIROSHIMA ,  MITSUHIRO OKUNE

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/3065 ,  H01L21/02 ,  H01L23/544 ,  H01L21/78

Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into element chips 10 by exposing the substrate to a first plasma. Therefore, element chips having a first surface, a second surface, and a side surface connecting the first surface and the second surface are held spaced from each other on a carrier. A protection film covering the element chip is formed only on the side surface and it is possible to suppress creep-up of a conductive material to the side surface in the mounting step by exposing the element chips to second plasma in which a mixed gas of fluorocarbon and helium is used as a raw material gas.

公开(公告)号：US20170069536A1

公开(公告)日：2017-03-09

申请号：US15245139

申请日：2016-08-23

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI HARIKAI ,  NORIYUKI MATSUBARA ,  HIDEO KANOU ,  MITSURU HIROSHIMA ,  SYOUZOU WATANABE ,  TOSHIHIRO WADA

IPC: H01L21/78 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L21/76826 ,  H01L21/78

Abstract: Provided is a plasma treatment method including: placing a substrate carrier holding a substrate on a stage; adjusting a distance between a cover and the stage to a first distance in which the cover covers a frame without coming into contact with the substrate carrier; performing a plasma treatment on the substrate placed on the stage after the adjusting of the distance; carrying the substrate together with the substrate carrier out from a reaction chamber after the performing of the plasma treatment; and removing an adhered substance adhered to the cover by generating plasma in the inside of the reaction chamber after the carrying of the substrate, in which the distance between the cover and the stage in the removing of the adhered substance is a second distance greater than the first distance.

Abstract translation: 提供了一种等离子体处理方法，包括：将保持衬底的衬底载体放置在平台上; 将盖和台架之间的距离调整到第一距离，其中盖子覆盖框架而不与基板载体接触; 在调整距离后，在放置在舞台上的基板上进行等离子体处理; 在执行等离子体处理之后将基板与基板载体一起从反应室中输出; 以及在承载基板之后，通过在反应室内部产生等离子体，除去附着在盖子上的附着物质，其中盖子和移除粘合物质的台阶之间的距离比第二距离大 第一距离

公开(公告)号：US20170263500A1

公开(公告)日：2017-09-14

申请号：US15426199

申请日：2017-02-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： BUNZI MIZUNO ,  SHOGO OKITA ,  MITSURU HIROSHIMA ,  TUTOMU SAKURAI ,  NORIYUKI MATSUBARA

IPC: H01L21/78 ,  H01L21/67

CPC classification number: H01L21/78 ,  H01J2237/334 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/67069 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/6831

Abstract: The method includes a laser scribing step of forming an opening including an exposing portion, where the first layer is exposed, by irradiating the dividing region of the substrate with laser light from the first main surface side, forming a remaining region on which the second layer in the dividing region remains around the opening other than the exposing portion, and forming a first damaged region of a surface layer portion of the first layer including the exposing portion and a second damaged region of a surface layer portion of the first layer to be covered by the remaining region on the first layer of the dividing region.

公开(公告)号：US20170092527A1

公开(公告)日：2017-03-30

申请号：US15258717

申请日：2016-09-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI HARIKAI ,  SHOGO OKITA ,  NORIYUKI MATSUBARA

IPC: H01L21/683 ,  H01L21/78

CPC classification number: H01L21/6836 ,  H01L21/78 ,  H01L23/3185 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: In a plasma processing process used for a method of manufacturing element chips by which a plurality of element chips are manufactured by dividing a substrate having a plurality of element regions, the substrate is exposed to first plasma, and thereby the substrate is divided into element chips, and the element chips having first surfaces, second surfaces, and side surfaces connecting the first surfaces to the second surfaces are held with an interval between the element chips on the carrier. The element chips are exposed to second plasma which uses a mixed gas of fluorocarbon and helium as a raw material gas, and thereby a protection film covering the side surfaces is formed, and a conductive material is prevented from creeping up to the side surfaces during a mounting process.

公开(公告)号：US20170263526A1

公开(公告)日：2017-09-14

申请号：US15427548

申请日：2017-02-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： BUNZI MIZUNO ,  MITSURU HIROSHIMA ,  SHOGO OKITA ,  NORIYUKI MATSUBARA ,  ATSUSHI HARIKAI

IPC: H01L23/31 ,  H01L21/78 ,  H01L21/428 ,  H01L21/56 ,  H01L21/311 ,  H01L23/544

CPC classification number: H01L23/3192 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/428 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2223/5446

Abstract: A method for manufacturing an element chip includes a protection film etching step of removing a part of the protection film which is stacked on the dividing region and the protection film which is stacked on the element region through etching the protection film anisotropically by exposing the substrate to first plasma and remaining the protection film for covering an end surface of the element region. Furthermore, the method for manufacturing an element chip includes an isotropic etching step of etching the dividing region isotropically by exposing the substrate to second plasma and a plasma dicing step of dividing the substrate to a plurality of element chips including the element region by exposing the substrate to third plasma in a state where the second main surface is supported by a supporting member.

公开(公告)号：US20170263525A1

公开(公告)日：2017-09-14

申请号：US15426341

申请日：2017-02-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： BUNZI MIZUNO ,  SHOGO OKITA ,  MITSURU HIROSHIMA ,  TUTOMU SAKURAI ,  NORIYUKI MATSUBARA

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/311 ,  H01L23/544 ,  H01L21/268 ,  H01L21/78

CPC classification number: H01L23/3192 ,  H01L21/268 ,  H01L21/31116 ,  H01L21/56 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L23/562 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381

Abstract: A method of manufacturing an element chip includes an isotropic etching step of removing the first damaged region and the second damaged region through etching the first layer isotropically by exposing the substrate to first plasma after the laser scribing step. The method of manufacturing an element chip further includes a plasma, dicing step of dividing the substrate to a plurality of element chips including the element region through etching the first layer anisotropically by exposing the substrate to second plasma in a state where the second main surface is supported by a supporting member, after the isotropic etching step.

公开(公告)号：US20170229385A1

公开(公告)日：2017-08-10

申请号：US15408770

申请日：2017-01-18

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI HARIKAI ,  SHOGO OKITA ,  NORIYUKI MATSUBARA

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3171 ,  H01L24/09 ,  H01L24/89 ,  H01L2224/80801 ,  H01L2924/15323

Abstract: To provide a method of manufacturing an element chip in which creep-up of a conductive material can be suppressed in a mounting step. In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by an insulating film, the substrate is divided into the element chips by exposing the substrate to a first plasma, the element chips having a first surface, a second surface, and a side surface are held spaced from each other on a carrier, and the side surface and the insulating film are in a state of being exposed.