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公开(公告)号：US08102651B2
公开(公告)日：2012-01-24
申请号：US12572301
申请日：2009-10-02
IPC分类号： H05K7/20
CPC分类号： G06F1/20
摘要： Method and apparatus providing airflow through a chassis including an upstream column of memory modules and a downstream column of memory modules. The airflow is divided into first and second separate airflow streams extending from an upstream end of the upstream column to a downstream end of the downstream column. The first airflow stream is guided into contact with a single memory module operably-installed in the upstream column and to avoid contact with any memory module in the downstream column. The second airflow stream is guided to avoid contact with any memory module in the upstream column and into contact with a single memory module operably-installed in the downstream column. The improved cooling enables the extended use of a single memory module per channel, even though the thermal load on such a memory module is greater. The result is an overall savings of power, since cooling requirements no longer dictate the installation of additional memory modules per channel in order to share and distribute the thermal load.
摘要翻译： 提供通过包括存储器模块的上游列和存储器模块的下游列的底盘的气流的方法和装置。 气流被分为从上游塔的上游端延伸到下游塔的下游端的第一和第二分开的气流。 第一气流引导与可操作地安装在上游塔中的单个存储器模块接触，并且避免与下游塔中的任何存储器模块接触。 引导第二气流流以避免与上游塔中的任何存储器模块接触并与可操作地安装在下游塔中的单个存储器模块接触。 即使在这样的存储器模块上的热负载较大，改进的冷却也能够每通道扩展使用单个存储器模块。 结果是总体上节省了电力，因为冷却要求不再要求每个通道安装额外的内存模块，以便共享和分配热负载。
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公开(公告)号：US20110080700A1
公开(公告)日：2011-04-07
申请号：US12572301
申请日：2009-10-02
IPC分类号： G06F1/20
CPC分类号： G06F1/20
摘要： Method and apparatus providing airflow through a chassis including an upstream column of memory modules and a downstream column of memory modules. The airflow is divided into first and second separate airflow streams extending from an upstream end of the upstream column to a downstream end of the downstream column. The first airflow stream is guided into contact with a single memory module operably-installed in the upstream column and to avoid contact with any memory module in the downstream column. The second airflow stream is guided to avoid contact with any memory module in the upstream column and into contact with a single memory module operably-installed in the downstream column. The improved cooling enables the extended use of a single memory module per channel, even though the thermal load on such a memory module is greater. The result is an overall savings of power, since cooling requirements no longer dictate the installation of additional memory modules per channel in order to share and distribute the thermal load.
摘要翻译： 提供通过包括存储器模块的上游列和存储器模块的下游列的底盘的气流的方法和装置。 气流被分为从上游塔的上游端延伸到下游塔的下游端的第一和第二分开的气流。 第一气流引导与可操作地安装在上游塔中的单个存储器模块接触，并且避免与下游塔中的任何存储器模块接触。 引导第二气流流以避免与上游塔中的任何存储器模块接触并与可操作地安装在下游塔中的单个存储器模块接触。 即使在这样的存储器模块上的热负载较大，改进的冷却也能够每通道扩展使用单个存储器模块。 结果是总体上节省了电力，因为冷却要求不再要求每个通道安装额外的内存模块，以便共享和分配热负载。
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3.发明授权公开(公告)号：US08607003B2
公开(公告)日：2013-12-10
申请号：US13183776
申请日：2011-07-15
IPC分类号： G06F12/06 , G06F13/378
CPC分类号： G06F9/3824 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0868 , G06F12/0891 , G06F2212/1016 , G06F2212/305 , G06F2212/311
摘要： Methods, apparatuses, and computer program products for memory access to a dual in-line memory module (DIMM) form factor flash memory are provided. Embodiments include receiving, by a controller from a processor through cacheable memory in the processor, a read request; transmitting, by the controller, the read request to the DIMM form factor flash memory; polling, by the controller, a read queue in the DIMM form factor flash memory until data is ready for the read request; copying from the DIMM form factor flash memory, by the controller, the data corresponding to the read request to a read queue in the controller; transmitting, by the controller on an interface between the controller and the processor, an invalidate command for the cacheable memory; and in response to receiving the invalidate command, reading by the processor the data stored in the read queue in the controller.
摘要翻译： 提供了用于存储器访问双列直插存储器模块（DIMM）形状因子闪存的方法，装置和计算机程序产品。 实施例包括由控制器从处理器通过处理器中的可缓存存储器接收读取请求; 由控制器将读请求传送到DIMM外形闪存; 由控制器轮询DIMM形状因子闪存中的读取队列，直到数据准备好读取请求; 通过控制器将与DIMM读写请求对应的数据从DIMM形状因子闪存复制到控制器中的读取队列; 由控制器在控制器和处理器之间的接口上发送用于可缓存存储器的无效命令; 并且响应于接收到无效命令，由处理器读取存储在控制器中的读取队列中的数据。
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公开(公告)号：US07984326B2
公开(公告)日：2011-07-19
申请号：US12465702
申请日：2009-05-14
IPC分类号： G06F11/00
CPC分类号： G11C29/08 , G11C5/04 , G11C29/88 , G11C2029/0407
摘要： Memory downsizing in a computer memory subsystem, the subsystem including one or more channels of computer memory with each channel including several Dual In-line Memory Modules (‘DIMMs’) and each DIMM capable of on-die termination (‘ODT’). Memory downsizing according to embodiments of the present invention includes identifying, during a memory initialization test in a Power On Self Test (‘POST’) by a firmware module, a defective DIMM of a particular channel in the computer memory subsystem and disabling, by the firmware module, the defective DIMM, including enabling ODT for the defective DIMM without disabling any non-defective DIMMs.
摘要翻译： 存储器在计算机存储器子系统中缩小尺寸，子系统包括一个或多个计算机存储器通道，每个通道包括几个双列直插存储器模块（“DIMM”）和每个能够进行片上端接（“ODT”）的DIMM。 根据本发明的实施例的存储器小型化包括在由固件模块进行的电源自检（“POST”）的存储器初始化测试期间识别计算机存储器子系统中特定通道的有缺陷的DIMM，并且通过 固件模块，有缺陷的DIMM，包括为有缺陷的DIMM启用ODT，而不会禁用任何无故障的DIMM。
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公开(公告)号：US20120173653A1
公开(公告)日：2012-07-05
申请号：US12981611
申请日：2010-12-30
申请人： Patrick M. Bland , John M. Borkenhagen , Thomas M. Bradicich , Dhruv M. Desai , Jimmy G. Foster, SR. , Joseph J. Jakubowski , Randolph S. Kolvick , Makoto Ono
发明人： Patrick M. Bland , John M. Borkenhagen , Thomas M. Bradicich , Dhruv M. Desai , Jimmy G. Foster, SR. , Joseph J. Jakubowski , Randolph S. Kolvick , Makoto Ono
IPC分类号： G06F15/167
CPC分类号： G06F9/4856
摘要： A computer program product and computer implemented method are provided for migrating a virtual machine between servers. The virtual machine is initially operated on a first server, wherein the first server accesses the virtual machine image over a network at a memory location within fabric attached memory. The virtual machine is migrated from the first server to a second server by flushing data to the virtual machine image from cache memory associated with the virtual machine on the first server and providing the state and memory location of the virtual machine to the second server. The virtual machine may then operate on the second server, wherein the second server accesses the virtual machine image over the network at the same memory location within the fabric attached memory without copying the virtual machine image.
摘要翻译： 提供了一种用于在服务器之间迁移虚拟机的计算机程序产品和计算机实现的方法。 虚拟机最初在第一服务器上操作，其中第一服务器通过网络在存储器内的存储器位置访问虚拟机映像。 通过从与第一服务器上的虚拟机相关联的高速缓存存储器将数据刷新到虚拟机映像，并将虚拟机的状态和存储器位置提供给第二服务器，从而将虚拟机从第一服务器迁移到第二服务器。 虚拟机然后可以在第二服务器上操作，其中第二服务器通过网络访问在结构连接存储器内的相同存储器位置处的虚拟机映像，而不复制虚拟机映像。
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6.发明申请公开(公告)号：US20130019048A1
公开(公告)日：2013-01-17
申请号：US13183776
申请日：2011-07-15
IPC分类号： G06F12/02
CPC分类号： G06F9/3824 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0868 , G06F12/0891 , G06F2212/1016 , G06F2212/305 , G06F2212/311
摘要： Methods, apparatuses, and computer program products for memory access to a dual in-line memory module (DIMM) form factor flash memory are provided. Embodiments include receiving, by a controller from a processor through cacheable memory in the processor, a read request; transmitting, by the controller, the read request to the DIMM form factor flash memory; polling, by the controller, a read queue in the DIMM form factor flash memory until data is ready for the read request; copying from the DIMM form factor flash memory, by the controller, the data corresponding to the read request to a read queue in the controller; transmitting, by the controller on an interface between the controller and the processor, an invalidate command for the cacheable memory; and in response to receiving the invalidate command, reading by the processor the data stored in the read queue in the controller.
摘要翻译： 提供了用于存储器访问双列直插存储器模块（DIMM）形状因子闪存的方法，装置和计算机程序产品。 实施例包括由控制器从处理器通过处理器中的可缓存存储器接收读取请求; 由控制器将读请求传送到DIMM外形闪存; 由控制器轮询DIMM形状因子闪存中的读取队列，直到数据准备好读取请求; 通过控制器将与DIMM读写请求对应的数据从DIMM形状因子闪存复制到控制器中的读取队列; 由控制器在控制器和处理器之间的接口上发送用于可缓存存储器的无效命令; 并且响应于接收到无效命令，由处理器读取存储在控制器中的读取队列中的数据。
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公开(公告)号：US20100293410A1
公开(公告)日：2010-11-18
申请号：US12465702
申请日：2009-05-14
CPC分类号： G11C29/08 , G11C5/04 , G11C29/88 , G11C2029/0407
摘要： Memory downsizing in a computer memory subsystem, the subsystem including one or more channels of computer memory with each channel including several Dual In-line Memory Modules (‘DIMMs’) and each DIMM capable of on-die termination (‘ODT’). Memory downsizing according to embodiments of the present invention includes identifying, during a memory initialization test in a Power On Self Test (‘POST’) by a firmware module, a defective DIMM of a particular channel in the computer memory subsystem and disabling, by the firmware module, the defective DIMM, including enabling ODT for the defective DIMM without disabling any non-defective DIMMs.
摘要翻译： 存储器在计算机存储器子系统中缩小尺寸，子系统包括一个或多个计算机存储器通道，每个通道包括几个双列直插存储器模块（“DIMM”）和每个能够进行片上端接（“ODT”）的DIMM。 根据本发明的实施例的存储器小型化包括在由固件模块进行的电源自检（“POST”）的存储器初始化测试期间识别计算机存储器子系统中特定通道的有缺陷的DIMM，并且通过 固件模块，有缺陷的DIMM，包括为有缺陷的DIMM启用ODT，而不会禁用任何无故障的DIMM。
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公开(公告)号：US07562247B2
公开(公告)日：2009-07-14
申请号：US11434611
申请日：2006-05-16
CPC分类号： G06F11/1604 , G06F11/20
摘要： Methods and systems are disclosed for providing independent clock failover for scalable blade servers that include assigning a server blade to one of a plurality of clock failover groups, providing a plurality of independent clock signals to the clock generator of the server blade, wherein one of the plurality of independent clock signals is an active clock signal, detecting a failover condition for the clock failover group assigned to the server blade, and switching the active clock signal, in response to the detected failover condition, from one independent clock signal to another independent clock signal.
摘要翻译： 公开了用于为可伸缩刀片服务器提供独立的时钟故障切换的方法和系统，包括将服务器刀片分配给多个时钟故障转移组中的一个，向服务器刀片的时钟发生器提供多个独立的时钟信号，其中， 多个独立时钟信号是活动时钟信号，检测分配给服务器刀片的时钟故障切换组的故障转移条件，并响应于检测到的故障转移条件将活动时钟信号从一个独立时钟信号切换到另一独立时钟 信号。
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9.发明授权Bridge for interfacing buses in computer system with a direct memory access controller having dynamically configurable direct memory access channels 失效用于在计算机系统中与具有可动态配置的直接存储器访问通道的直接存储器访问控制器接口的桥
公开(公告)号：US5561820A
公开(公告)日：1996-10-01
申请号：US351220
申请日：1994-11-30
申请人： Patrick M. Bland , Daniel R. Cronin, III , Richard G. Hofmann , Dennis Moeller , Lance M. Venarchick
发明人： Patrick M. Bland , Daniel R. Cronin, III , Richard G. Hofmann , Dennis Moeller , Lance M. Venarchick
CPC分类号： G06F13/28 , G06F13/4027
摘要： A bridge interface for buses in a computer system has a direct memory access (DMA) controller that controls memory transfers in the computer system. The DMA controller has a pair of cascaded DMA controller chips that provide a plurality of DMA channels. A multiplexer circuit receives memory address signals from the DMA controller chips. The memory address signals are received in both a shifted form and an unshifted form at the multiplexer inputs. By selection of the shifted or the unshifted memory address at the multiplexer, either even or odd addresses are produced at the multiplexer output for each DMA channel, thereby selectively providing 8-bit or 16-bit memory accesses. The control of the multiplexer is programmable for each DMA channel, providing dynamic configuration of the DHA channels as either 8-bit or 16-bit channels.
摘要翻译： 用于计算机系统中总线的桥接口具有控制计算机系统中的存储器传输的直接存储器访问（DMA）控制器。 DMA控制器具有一对提供多个DMA通道的级联DMA控制器芯片。 多路复用器电路从DMA控制器芯片接收存储器地址信号。 存储器地址信号在多路复用器输入端以移位形式和非移相形式被接收。 通过选择多路复用器处的移位或未移位的存储器地址，在多路复用器输出处产生偶数或奇数地址，用于每个DMA通道，由此选择性地提供8位或16位存储器访问。 多路复用器的控制可针对每个DMA通道进行编程，提供DHA通道作为8位或16位通道的动态配置。
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10.发明授权Data processing apparatus for dynamically setting timings in a dynamic memory system 失效用于在动态存储器系统中动态地设置定时的数据处理装置
公开(公告)号：US5522064A
公开(公告)日：1996-05-28
申请号：US590978
申请日：1990-10-01
IPC分类号： G11C11/401 , G06F12/00 , G06F12/02 , G06F12/06 , G06F13/42 , G11C11/407 , G06F1/06 , G06F1/04 , G06F1/08
CPC分类号： G06F13/4243
摘要： A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs (Single In-line Memory Modules) that differ in size and speed of operation. The memory controller is operable, in response to an access request for a given SIMM, to read from a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS (Row Address Strobe) to CAS (Column Address Strobe) time, and CAS pulse width, depending on the SIMM being accessed.
摘要翻译： 数据处理系统包括存储器控制器，用于访问动态存储器，该动态存储器具有大小和操作速度不同的多个SIMM（单列直插存储器模块）。 响应于给定SIMM的访问请求，存储器控制器可操作地从SIMM定义寄存器读取并且根据所访问的特定SIMM的定时要求动态地产生存储器访问信号。 每次访问SIMM时都会设置这些信号。 这些信号根据正在访问的SIMM提供RAS预充电时间，RAS（行地址选通）到CAS（列地址选通）时间的不同时钟周期和CAS脉冲宽度。
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