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16 条记录 (耗时 0.017 秒)

    Connection between an I/O region and the core region of an integrated circuit
    1.
    发明申请
    Connection between an I/O region and the core region of an integrated circuit 有权
    I / O区域与集成电路的核心区域之间的连接

    公开(公告)号：US20080164615A1

    公开(公告)日：2008-07-10

    申请号：US11651614

    申请日：2007-01-08

    申请人： Paul Lassa ,  Paul Paternoster ,  Brian Cheung

    发明人： Paul Lassa ,  Paul Paternoster ,  Brian Cheung

    IPC分类号： H01L23/52

    CPC分类号： H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A connection between a first circuit within an I/O region of an integrated circuit chip and a second circuit within a core region of the chip. The first circuit is connected to a bonding pad through a first conductor in a first layer of an I/O region. The second circuit is connected to the bonding pad through a second conductor in a second layer of an I/O region above the first layer.

    摘要翻译： 集成电路芯片的I / O区域内的第一电路与芯片的芯区域内的第二电路之间的连接。 第一电路通过I / O区域的第一层中的第一导体连接到焊盘。 第二电路通过位于第一层上方的I / O区域的第二层中的第二导体连接到焊盘。

    Connection between an I/O region and the core region of an integrated circuit
    2.
    发明授权
    Connection between an I/O region and the core region of an integrated circuit 有权
    I / O区域与集成电路的核心区域之间的连接

    公开(公告)号：US08304813B2

    公开(公告)日：2012-11-06

    申请号：US11651614

    申请日：2007-01-08

    申请人： Paul Lassa ,  Paul Paternoster ,  Brian Cheung

    发明人： Paul Lassa ,  Paul Paternoster ,  Brian Cheung

    IPC分类号： H01L27/118

    CPC分类号： H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A connection between a first circuit within an I/O region of an integrated circuit chip and a second circuit within a core region of the chip. The first circuit is connected to a bonding pad through a first conductor in a first layer of an I/O region. The second circuit is connected to the bonding pad through a second conductor in a second layer of an I/O region above the first layer.

    摘要翻译： 集成电路芯片的I / O区域内的第一电路与芯片的芯区域内的第二电路之间的连接。 第一电路通过I / O区域的第一层中的第一导体连接到焊盘。 第二电路通过位于第一层上方的I / O区域的第二层中的第二导体连接到焊盘。

    De-Glitch Circuit
    3.
    发明申请
    De-Glitch Circuit 有权
    去毛刺电路

    公开(公告)号：US20080164909A1

    公开(公告)日：2008-07-10

    申请号：US11686828

    申请日：2007-03-15

    申请人： Darmin Jin ,  Brian Cheung

    发明人： Darmin Jin ,  Brian Cheung

    IPC分类号： G06F7/38 ,  H03K19/173

    CPC分类号： H03K5/1252

    摘要： A digital logic circuit and method for de-glitching an input signal. The circuit removes distortion that occurs during a “de-glitching” time period that follows each transition of the input signal from 0 to 1 or from 1 to 0. The circuit can remove such distortion from the input signal without substantially delaying the input signal. Specifically, the delay interposed can be much less than the duration of the de-glitching time period. One embodiment includes first and second Set-Reset flip-flops each having an input connected to receive the input signal and having an output connected to a majority circuit. A delay circuit also receives the input signal and provides an output to the majority circuit. Other embodiments replace the majority circuit with a circuit including logic gates.

    摘要翻译： 一种用于对输入信号进行去毛刺的数字逻辑电路和方法。 电路消除了在输入信号从0到1或从1到0之间的每个转换之后的“去毛刺”时间段期间发生的失真。该电路可以从输入信号中去除这种失真而基本上不延迟输入信号。 具体地说，插入的延迟可以远小于除毛时间段的持续时间。 一个实施例包括第一和第二设置复位触发器，每个触发器具有连接的输入端以接收输入信号并且具有连接到多数电路的输出。 延迟电路还接收输入信号并向多数电路提供输出。 其他实施例用包括逻辑门的电路代替多数电路。

    Integrated Circuits and Methods with Two Types of Decoupling Capacitors
    5.
    发明申请
    Integrated Circuits and Methods with Two Types of Decoupling Capacitors 有权
    具有两种去耦电容器的集成电路和方法

    公开(公告)号：US20080237647A1

    公开(公告)日：2008-10-02

    申请号：US11967778

    申请日：2007-12-31

    申请人： Brian Cheung ,  Emmanuel de Muizon

    发明人： Brian Cheung ,  Emmanuel de Muizon

    IPC分类号： H01L27/10 ,  H01L29/94

    CPC分类号： H01L27/0805 ,  H01L27/0811

    摘要： Methods and systems for optimal decoupling capacitance in a dual-voltage power-island architecture. In low-voltage areas of the chip, accumulation capacitors of two different types are used for decoupling, depending on whether the capacitor is located in an area which is always-on or an area which is conditionally powered.

    摘要翻译： 双电源电力岛结构中最佳去耦电容的方法和系统。 在芯片的低电压区域中，根据电容器是位于始终接通的区域还是有条件供电的区域，使用两种不同类型的累积电容器进行去耦。

    Method of fabricating a field effect transistor
    6.
    发明授权
    Method of fabricating a field effect transistor 失效
    制作场效应晶体管的方法

    公开(公告)号：US6090716A

    公开(公告)日：2000-07-18

    申请号：US767708

    申请日：1996-12-17

    申请人： Brian H. Floyd ,  Chin H. Ho ,  Mike F. Chang ,  Min Juang ,  Brian Cheung ,  Karen Lee

    发明人： Brian H. Floyd ,  Chin H. Ho ,  Mike F. Chang ,  Min Juang ,  Brian Cheung ,  Karen Lee

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/311

    CPC分类号： H01L29/7827

    摘要： In the present method, a semiconductor substrate is provided with an epitaxial layer thereon. A source/drain region is provided in a portion of the epitaxial layer, and a plurality of trenches are etched in the epitaxial layer and extend into the substrate, to define a plurality of mesas.An oxide layer of generally uniform thickness is provided over the mesas and in the trenches, and a polysilicon layer is provided over the oxide layer and is etched so that the oxide layer overlying the mesas is exposed, and the top surface of the polysilicon within the trenches is below the level of the tops of the mesas.A layer of spin-on-glass (SOG) is provided, and the SOG layer and oxide layer are etched substantially to the level of the tops of the mesas, to expose the tops of the mesas and to leave the portions of the SOG over the respective polysilicon portions in the trenches substantially coplaner with the tops of the mesas.A conductive layer is provided over the remaining portions of the SOG layer and the tops of the mesas.

    摘要翻译： 在本方法中，在半导体衬底上设置有外延层。 源极/漏极区域设置在外延层的一部分中，并且在外延层中蚀刻多个沟槽并延伸到衬底中以限定多个台面。 在台面和沟槽中设置大致均匀厚度的氧化物层，并且在氧化物层上方设置多晶硅层，并且被蚀刻，使得覆盖在台面上的氧化物层被暴露，并且多晶硅的顶表面在 沟渠低于台面顶部的水平。 提供了一层旋涂玻璃（SOG），SOG层和氧化物层被基本蚀刻到台面顶部的水平面，露出台面的顶部，并使SOG的部分过去 沟槽中的各个多晶硅部分与台面的顶部基本上共面。 导电层设置在SOG层的剩余部分和台面的顶部之上。

    CMOS Differential driver circuit for high offset ground
    7.
    发明授权
    CMOS Differential driver circuit for high offset ground 失效
    CMOS差分驱动电路，用于高偏移地

    公开(公告)号：US5491432A

    公开(公告)日：1996-02-13

    申请号：US927097

    申请日：1992-08-07

    申请人： Anthony Y. Wong ,  Eric Chan ,  Brian Cheung ,  Daniel Wong

    发明人： Anthony Y. Wong ,  Eric Chan ,  Brian Cheung ,  Daniel Wong

    IPC分类号： G06F3/00 ,  H03K5/151 ,  H03K17/687 ,  H03K17/693 ,  H03K19/0175 ,  H04L25/02 ,  H03K19/0185 ,  H03K19/0948

    CPC分类号： H03K5/151

    摘要： A CMOS driver circuit which differentially drives a pair of transmission lines at a first terminal in response to a signal on the CMOS driver circuit's input terminal for reception of said signal at a second terminal is provided. The driver circuit has two pairs of drive transistors. Each drive transistor has first and second source/drains and a gate. Each drive transistor pair is connected to one of said transmission line pair, and has a NMOS transistor and a PMOS transistor.

    摘要翻译： 提供了CMOS驱动器电路，其响应于CMOS驱动器电路的输入端上的信号在第一端子差分地驱动一对传输线，用于在第二端子处接收所述信号。 驱动电路有两对驱动晶​​体管。 每个驱动晶体管具有第一和第二源极/漏极和栅极。 每个驱动晶体管对连接到所述传输线对之一，并且具有NMOS晶体管和PMOS晶体管。

    Integrated circuits and methods with two types of decoupling capacitors
    8.
    发明授权
    Integrated circuits and methods with two types of decoupling capacitors 有权
    具有两种去耦电容的集成电路和方法

    公开(公告)号：US07898013B2

    公开(公告)日：2011-03-01

    申请号：US11967778

    申请日：2007-12-31

    申请人： Brian Cheung ,  Emmanuel De Muizon

    发明人： Brian Cheung ,  Emmanuel De Muizon

    IPC分类号： H01L29/94

    CPC分类号： H01L27/0805 ,  H01L27/0811

    摘要： Methods and systems for optimal decoupling capacitance in a dual-voltage power-island architecture. In low-voltage areas of the chip, accumulation capacitors of two different types are used for decoupling, depending on whether the capacitor is located in an area which is always-on or an area which is conditionally powered.

    摘要翻译： 双电源电力岛结构中最佳去耦电容的方法和系统。 在芯片的低电压区域中，根据电容器是位于始终接通的区域还是有条件供电的区域，使用两种不同类型的累积电容器进行去耦。

    APPARATUS AND METHOD FOR HIGH VOLTAGE SWITCHES
    10.
    发明申请
    APPARATUS AND METHOD FOR HIGH VOLTAGE SWITCHES 有权
    高压开关的装置和方法

    公开(公告)号：US20130300485A1

    公开(公告)日：2013-11-14

    申请号：US13468957

    申请日：2012-05-10

    申请人： Darmin Jin ,  William Chau ,  Brian Cheung

    发明人： Darmin Jin ,  William Chau ,  Brian Cheung

    IPC分类号： H03L5/00 ,  H03K17/56

    CPC分类号： G01R31/31924 ,  H03K17/56 ,  H03K19/017509 ,  H03K2217/0081

    摘要： Apparatus and method for coupling high voltages for a semiconductor device via high voltage switches are disclosed. A high voltage switch includes a switch and a level shifter. The switch is defined between a voltage source and a voltage output. An enable line is coupled to a first transistor of the switch. The level shifter includes an input and an output. A characterization line is coupled to the input of the level shifter and the output of the level shifter is coupled to a second transistor of the switch. The level shifter further includes a power rail that is coupled to the switch between the first transistor and the second transistor.

    摘要翻译： 公开了一种用于通过高压开关耦合半导体器件的高电压的装置和方法。 高压开关包括开关和电平转换器。 开关定义在电压源和电压输出之间。 使能线耦合到开关的第一晶体管。 电平移位器包括输入和输出。 表征线耦合到电平移位器的输入，并且电平移位器的输出耦合到开关的第二晶体管。 电平移位器还包括电源轨，该电源轨耦合到第一晶体管和第二晶体管之间的开关。